Webinar - Understanding RISC-V Architecture and Implementation on an FPGA

In DigiKey’s upcoming webinar, speaker Sarah L. Harris, Associate Professor of Electrical and Computer Engineering at the University of Nevada, will teach attendees about the RISC-V (pronounced risk five) processor core. Topics covered will include programming, memory hierarchy, and implementation on an FPGA.

Please join us on February 23, 2022 at 2:00 PM CST. Can’t make it? That’s ok! Everyone who registers will receive a recording after it’s over.

Click here to register today: https://event.on24.com/wcc/r/3606359/8C64559CCB740EBD2485729CD7151AE8?partnerref=blog