STMicroelectronics의 STP04CM05 규격서

I ’l Meaugmented TSSOP16 (Exposed pad)
January 2016
DocID14191 Rev 6
1/22
This is information on a product in full production.
www.st.com
STP04CM05
4-bit constant current power-LED sink driver
Datasheet - production data
Features
4 constant current output channels
Adjustable output current through one
external resistor
Can be driven by a 3.3 V microcontroller
Serial data IN/parallel data OUT
Output current: 80-400 mA
20 V of output driving capability
30 MHz clock frequency
UVLO (under voltage lockout) and POR
(power ON reset)
TSD, thermal shutdown, output off when
junction temperature exceeds limit
Operating free-air temperature range -40° to
125 °C
ESD protection 2.5 kV HBM, 200 V MM
Available in high thermal TSSOP exposed
pad
Description
The STP04CM05 is a high-power LED driver and
4-bit shift register designed for Power-LED
applications.
The STP04CM05 contains a 4-bit serial IN,
parallel OUT shift register that feeds a 4-bit D-
type storage register. In the output stage, four
regulated current sources were designed to
provide 80-400 mA constant current to drive high
power LEDs.
The STP04CM05 guarantees 20 V output driving
capability, allowing users to connect more LEDs
in series. The high clock frequency, 30 MHz, also
satisfies the system requirements which include
high volume data transmission.
The STP04CM05 is well suited for very high
brightness displays and special lighting
applications.
The STP04CM05 is offered in TSSOP16
exposed pad packages.
Table 1: Device summary
Order code
Packing
STP04CM05XTTR
TSSOP16 exposed pad (tape and reel)
2500 parts per reel
Contents
STP04CM05
2/22
DocID14191 Rev 6
Contents
1 Internal schematic ........................................................................... 3
2 Pin settings ...................................................................................... 4
2.1 Pin connection ................................................................................... 4
2.2 Pin description ................................................................................... 4
3 Maximum rating ............................................................................... 5
3.1 Thermal data ..................................................................................... 5
3.2 Recommended operating conditions ................................................. 6
4 Electrical characteristics ................................................................ 7
5 Equivalent circuit and outputs ....................................................... 9
6 Timing diagrams ............................................................................ 11
7 Test circuit ..................................................................................... 14
8 Typical characteristics .................................................................. 15
9 Package information ..................................................................... 17
9.1 TSSOP16 exposed pad package information ................................. 18
9.2 TSSOP16 exposed pad packing information .................................. 20
10 Revision history ............................................................................ 21
uvLc k FOR RiEXY w-meo uuro ouu 0.19pm Enum- 4X Dam Lmah 4x shm mun ours Vna Gwnoamzmsnswr
STP04CM05
Internal schematic
DocID14191 Rev 6
3/22
1 Internal schematic
Figure 1: Block diagram
GND GND sow CLK LE m W N‘C, ‘[ ]IE 2[ ]Is 1[ ]IA 4[ ]I: 5[ ]12 s[ ]n 7[ ]m a[ ]9 TSSOP16 (exposed pad) v REXI 500 (E N.C‘ m m N.C‘ m2 ewummmswzzaw
Pin settings
STP04CM05
4/22
DocID14191 Rev 6
2 Pin settings
2.1 Pin connection
Figure 2: Pin connection
The exposed pad should be attached to a metal land electrically isolated or
connected to ground.
2.2 Pin description
Table 2: Pin description
TSSOP16 exposed pad pin N°
Symbol
Name and function
1, 2
GND
Ground terminal
3
SDI
Serial data input terminal
4
CLK
Clock input terminal
5
LE
Latch input terminal
6
OUT 0
Output terminal
7
OUT 1
Output terminal
8, 9, 12
N.C.
Not connected
10
OUT 2
Output terminal
11
OUT 3
Output terminal
13
OE
Output enable input terminal (active low)
14
SDO
Serial data out terminal
15
R-EXT
Constant current programming
16
VDD
5 V supply voltage terminal
STP04CM05
Maximum rating
DocID14191 Rev 6
5/22
3 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
500
mA
VI
Input voltage
-0.4 to VDD+0.4
V
IGND
GND terminal current
2000
mA
fCLK
Clock frequency
50
MHz
TOPR
Operating temperature range
-40 to +125
°C
TSTG
Storage temperature range
-55 to +150
°C
3.1 Thermal data
Table 4: Thermal data
Symbol
Parameter
TSSOP16 exposed pad
Unit
RthJA
Thermal resistance junction-ambient
37.5 (1)
°C/W
Notes:
(1) Using the PCB multi-layer JEDEC Standard test boards.
Maximum rating
STP04CM05
6/22
DocID14191 Rev 6
3.2 Recommended operating conditions
Table 5: Recommended operating conditions
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VDD
Supply voltage
3.3
5.0
5.5
V
VO
Output voltage
19
V
IO
Output current
OUTn VDD = 5 V
80
400
mA
IOH
Output current
Serial-OUT
+1
mA
IOL
Output current
Serial-OUT
-1
mA
VIH
Input voltage
0.7
VDD
VDD+0.3
V
VIL
Input voltage
-0.3
0.3 VDD
V
twEN
OE pulse width
VDD = 5 V, IO = 350 mA
80
50
ns
VDD = 3.3 V, IO = 350 mA
250
150
twLAT
LE pulse width
VDD = 3.0 to 3.6 V
8
4
ns
twCLK
CLK pulse width
8.5
7.5
ns
tSETUP(D)
Setup time for DATA
8.5
7.5
ns
tHOLD(D)
Hold time for DATA
8.5
7.5
ns
tSETUP(L)
Setup time for LATCH
8.5
7.0
ns
tHOLD(E)
Hold time for ENABLE
8.5
7.0
ns
fCLK
Clock frequency
Cascade operation (1)
30
MHz
TOPR
Operating temperature
range
-40
+125
°C
Notes:
(1) If multiple devices are cascaded, it may not be possible achieve the maximum data transfer. Please consider
the timing conditions carefully.
STP04CM05
Electrical characteristics
DocID14191 Rev 6
7/22
4 Electrical characteristics
TA = 25 °C, unless otherwise specified.
Table 6: Current accuracy
Output voltage
Current accuracy
Output current
Between bits
Between ICs
≥ 1.4 V
Typ. ± 1%
± 6%
80 to 400 mA
Table 7: Electrical characteristics (VDD = 3.3 to 5 V)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIH
Input voltage high
level
0.7
VDD
VDD
V
VIL
Input voltage low
level
GND
0.3
VDD
V
IOH
Output leakage
current
VOH = 19 V
10
μA
VOL
Output voltage
(serial-OUT)
IOL = 1 mA
0.4
V
VOH
Output voltage
(serial-OUT)
IOH = -1 mA
VDD-
0.4 V
V
IOL1
Output current
VO = 0.3 VREXT = 980 Ω
75.2
80
84.8
mA
IOL2
VO = 1.2 VREXT = 190 kΩ
376
400
424
mA
ΔIOL1
Output current error
between bit
(all output ON)
VO = 0.3 VREXT = 980 Ω
IO = 80 mA
1
1.5
%
ΔIOL2
VO = 1.2 VREXT = 190 Ω
IO = 400 mA
1
1.5
%
RSIN(up)
Pull-up resistor
150
300
600
kΩ
RSIN(down)
Pull-down resistor
100
200
400
kΩ
IDD(OFF1)
Supply current
(OFF)
REXT = OPEN OUT 0 to 3 = OFF
1
1.5
mA
IDD(OFF2)
REXT = 980 Ω OUT 0 to 3 = OFF
3.8
6
IDD(OFF3)
REXT = 190 Ω OUT 0 to 3 = OFF
14
18.5
IDD(ON1)
Supply current (ON)
REXT = 980 Ω OUT 0 to 3 = ON
4.0
6.0
IDD(ON2)
REXT = 190 Ω OUT 0 to 3 = ON
14.5
19
Electrical characteristics
STP04CM05
8/22
DocID14191 Rev 6
Table 8: Switching characteristics (VDD = 3.3 to 5 V)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tPLH1
Propagation delay time,
CLK- OUTn LE = H,
/OE = L
RL = 5.0 Ω
CL = 10 pF
IO = 350 mA
REXT = 224 Ω
VL = 3.0 V
VDD = 3.3 V
-
290
377
VDD = 5 V
-
200
260
ns
tPLH2
Propagation delay time,
LE- OUTn , / OE = L
VDD = 3.3 V
-
200
260
VDD = 5 V
-
140
180
ns
tPLH3
Propagation delay time,
/OE - OUTn , LE = H
VDD = 3.3 V
-
240
310
ns
VDD = 5 V
-
170
220
tPLH
Propagation delay time,
CLK-SDO
VDD = 3.3 V
-
25
35
VDD = 5 V
-
15
20
ns
tPHL1
Propagation delay time,
CLK- OUTn LE = H,
/OE = L
VDD = 3.3 V
-
49
64
VDD = 5 V
-
36
47
ns
tPHL2
Propagation delay time,
LE - OUTn , / OE = L
VDD = 3.3 V
-
39
51
VDD = 5 V
-
26
34
ns
tPHL3
Propagation delay time,
/OE - OUTn LE = H
VDD = 3.3 V
-
48
62
ns
VDD = 5 V
-
32
42
tPHL
Propagation delay time,
CLK-SDO
VDD = 3.3 V
-
30
39
VDD = 5 V
-
19
25
ns
tON
Output rise time 10~90% of
voltage waveform
VDD = 3.3 V
-
880
1150
VDD = 5 V
-
616
800
ns
tOFF
Output fall time 90~10% of
voltage waveform
VDD = 3.3 V
-
18
24
VDD = 5 V
-
14
18
ns
tr
CLK rise time (1)
VO = 5.0 V
REXT = 224 Ω
-
5000
ns
tf
CLK fall time (1)
-
5000
ns
Notes:
(1) In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
R019) =3OOKQ OE fl . 3K0 GND VDD LE fl 3K0 mefizoom GND cu 51902 swmzwzmsmow
STP04CM05
Equivalent circuit and outputs
DocID14191 Rev 6
9/22
5 Equivalent circuit and outputs
Figure 3: OE terminal
Figure 4: LE terminal
VDD C CLK,SD| O ._. o 1K0 GND 0 cslsmz VDD 4'h - . o 500 K GND 05151201 Gwmzmzuumnw E]
Equivalent circuit and outputs
STP04CM05
10/22
DocID14191 Rev 6
Figure 5: CLK, SDI terminal
Figure 6: SDO terminal
CLK SDI LE OE cum OUTI OUYZ OUTS sDo HIGH 0V HIGN 0v HIGH 0V HIGH 0v OFF ON OFF ON on ON 0;; [IN HIGH 0V ~— awmmzmsunw
STP04CM05
Timing diagrams
DocID14191 Rev 6
11/22
6 Timing diagrams
Figure 7: Timing diagram
1 Latch and output enable are level sensitive and are not synchronized with rising-
or-falling edge of CLK signal.
2 When LE terminal is low level, the latch circuit hold previous set of data.
3 When LE terminal is high level, the latch circuit refresh new set of data from SDI
chain.
4 When OE terminal is at low level, the output terminal - Out 0 to Out 03 respond
to data in the latch circuits, either ‘1’ for ON or ‘0’ for OFF.
5 When OE terminal is at high level, all output terminals will be switched OFF.
m sex sex hum sm 50x 50x 0mm 500 50x 0m flm GIPD300970151139MT
Timing diagrams
STP04CM05
12/22
DocID14191 Rev 6
Figure 8: Clock, serial-in, serial-out
on sex SDI / \ 'scrun LE 50): sex “In: Mon 'o_: 50x 50x 'muu own sax 'nu/MM 'm/fiuu has/Mu: as use qumnzmsmstT OFF OUTn 0N (3511070 exposnogzmsmsw
STP04CM05
Timing diagrams
DocID14191 Rev 6
13/22
Figure 9: Clock, serial-in, latch, enable, outputs
Figure 10: Outputs
loo; —__— |0L Von ouro To 0— E IIL-lm /0 cm '1 out: 40 VIL.VIH SDI R-EXT 6ND 50° 4° lair; __ cswaw slPDulazmsagasMT RL Von oura E WORD CLK CL GENERATOR RL LE OUYJ SDI :47sz GND 500 1- CL I“ I VL cslum GwmzmzmstnMT K17
Test circuit
STP04CM05
14/22
DocID14191 Rev 6
7 Test circuit
Figure 11: DC characteristic
Figure 12: AC characteristic
p... yew «am mm mm 1709 m m 2:» 1m 1m 3M 4m mo .na “no 1200 A1000 800 600 400 vamp MN m.» firm 20° vna:33v 50v 0 0 5a 100 15a me 250 300 :51: M10 450 own 5...: m but (MA) qwnmmmsww Gwmmzmsuwv man A 1m) < e="" _a="" 10="" 1="" 0="" 0.2="" 0.‘="" 0.6="" 0.3="" a="" -.="" idl="" i="" g‘pd131020150926mt="" vl="" (nate)="" lzwuzuz:="" vnn="33m5v" vozoammv="" 7'="" n-m="" mm:="" mm="" mm.="" mm="" j—l="" v:="" om100khz="" g‘pd13102d‘50931mt="">
STP04CM05
Typical characteristics
DocID14191 Rev 6
15/22
8 Typical characteristics
Figure 13: Output current-REXT resistor
Figure 14: Output current vs dropout voltage
Figure 15: Output current vs ± ΔIOL(%)
Figure 16: Four power-LED typ. application circuit
VL will be determined by the VF of the LEDs.
Condition: TA = 25 °C, Vdd = 5 V,VL = 3 V, Rext = 227 Ω.
swam um suayw awmzxazmsosaaw
Typical characteristics
STP04CM05
16/22
DocID14191 Rev 6
Figure 17: tON
Figure 18: tOFF
STP04CM05
Package information
DocID14191 Rev 6
17/22
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
WV; j/ p 4 Z 025 mm GAUGE PLAN 5% i: mzja QZEEW CDC N A‘U T A A‘L F T N E W W P 7419275 c
Package information
STP04CM05
18/22
DocID14191 Rev 6
9.1 TSSOP16 exposed pad package information
Figure 19: TSSOP16 exposed pad package outline
STP04CM05
Package information
DocID14191 Rev 6
19/22
Table 9: TSSOP16 exposed pad package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
1.10
A1
0.05
0.15
A2
0.85
0.90
0.95
b
0.19
0.30
c
0.09
0.20
D
5.00
D1
ACCORDING TO PAD SIZE
E
6.40
E1
4.30
4.40
4.50
E2
ACCORDING TO PAD SIZE
e
0.65
L
0.50
0.60
0.70
L1
1.00
k
8
aaa
0.076
— PO > \ I I " \ H Ac: p Nma' Drawmg mm w my»;
Package information
STP04CM05
20/22
DocID14191 Rev 6
9.2 TSSOP16 exposed pad packing information
Figure 20: TSSOP16 exposed pad tape and reel outline
Table 10: TSSOP16 exposed pad packing mechanical data
Dim.
mm
inch
Min.
Typ.
Max.
Min.
Typ.
Max.
A
330
12.992
C
12.8
13.2
0.504
0.519
D
20.2
0.795
N
60
2.362
T
22.4
0.882
Ao
6.7
6.9
0.264
0.272
Bo
5.3
5.5
0.209
0.217
Ko
1.6
1.8
0.063
0.071
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
STP04CM05
Revision history
DocID14191 Rev 6
21/22
10 Revision history
Table 11: Document revision history
Date
Revision
Changes
26-Nov-2007
1
Initial release
16-Jan-2008
2
Added: Figure 15 on page 15 and Figure 19 on page 17,
Updated: Table 8 on page 8.
12-Mar-2008
3
Updated: Figure 8 on page 12.
23-Jun-2008
4
Updated: Table 1 on page 1, Figure 21 on page 20.
07-Jun-2010
5
Updated: Note: on page 4, Table 10 on page 19.
07-Jan-2016
6
Removed SO-14 package.
Updated Figure 5: "CLK, SDI terminal".
Minor text changes.
STP04CM05
22/22
DocID14191 Rev 6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved