ST7MC1xx,2xx Datasheet by STMicroelectronics

April 2009 Rev 13 1/309

ST7MC1xx/ST7MC2xx

8-bit MCU with nested interrupts, Flash, 10-bit ADC,

brushless motor control, five timers, SPI, LINSCI™

Features

■Memories

– 8K to 60K dual voltage Flash Program memo-

ry or ROM with read-out protection capability,

In-application programming and In-circuit pro-

gramming.

– 384 to 1.5K RAM

– HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■Clock, reset and supply management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator os-

cillators and by-pass for external clock, clock

security system.

– Four power saving modes: Halt, Active-halt,

Wait and Slow

■Interrupt management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– MCES top level interrupt pin

– 16 external interrupt lines (on 3 vectors)

■Up to 60 I/O ports

– up to 60 multifunctional bidirectional I/O lines

– up to 41 alternate function lines

– up to 12 high sink outputs

■5 timers

– Main clock controller with: Real-time base,

Beep and clock-out capabilities

– Configurable window watchdog timer

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM and

pulse generator modes

– 8-bit PWM Auto-reload timer with: 2 input cap-

tures, 4 PWM outputs, output compare and

time base interrupt, external clock with

event detector

■2 Communication interfaces

– SPI synchronous serial interface

–LINSCI™ asynchronous serial interface

■Brushless motor control peripheral

– 6 high sink PWM output channels for sine-

wave or trapezoidal inverter control

– Motor safety including asynchronous emer-

gency stop and write-once registers

– 4 analog inputs for rotor position detection

(sensorless/hall/tacho/encoder)

– Permanent magnet motor coprocessor includ-

ing multiplier, programmable filters, blanking

windows and event counters

– Operational amplifier and comparator for cur-

rent/voltage mode regulation and limitation

■Analog peripheral

– 10-bit ADC with 16 input pins

■In-circuit Debug

■Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode de-

tection

– 17 main Addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

■Development tools

– Full hardware/software development package

Table 1. Device summary

Note 1: For development only. No production

LQFP64

14 x 14

LQFP80

14 x 14

LQFP32 7x 7LQFP44

10 x 10

Features ST7MC1K2 / ST7MC1K4 ST7MC2N6 1)/ ST7MC2S4 / ST7MC2S6 / ST7MC2S7 / ST7MC2S9

/ ST7MC2R6 / ST7MC2R7 / ST7MC2R9 / ST7MC2M9

Program memory - bytes 8K 16K 16K 32K 48K 60K

RAM (stack) - bytes 384 (256) 768 (256) 768 (256) 1024 (256) 1536 (256)

Peripherals Watchdog, 16-bit Timer A, LINSCI™, 10-bit ADC, MTC, 8-bit PWM ART, ICD

-SPI, 16-bit Timer B

Operating

Supply vs. Frequency 4.5 to 5.5V with fCPU≤ 8MHz

Temperature Range -40°C to +85°C

/-40°C to +125°C

-40°C to

+85°C

-40°C to +85°C

-40°C to +125°C -40°C to +85 °C -40°C to

+125°C

Package LQFP32 LQFP32 LQFP44 SDIP561)/LQFP64 LQFP64/44 LQFP80/64 LQFP44

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) . 37

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 47

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 107

10.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

10.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 271

12.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

12.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 290

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 292

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

15.1 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 300

15.3 TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 300

15.4 LINSCI LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

15.5 MISSING DETECTION OF BLDC “Z EVENT” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

15.6 INJECTED CURRENT ON PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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15.7 RESET VALUE OF UNAVAILABLE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

15.8 MAXIMUM VALUES OF AVD THRESHOLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

15.9 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 299.

X 3 3 3

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1 INTRODUCTION

The ST7MCx device is member of the ST7 micro-

controller family designed for mid-range applica-

tions with a Motor Control dedicated peripheral.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH, ROM or

FASTROM program memory.

Under software control, all devices can be placed

in Wait, Slow, Active-halt or Halt mode, reducing

power consumption when the application is in idle

or stand-by state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

VPP CONTROL

PROGRAM

(8K - 60K Bytes)

VDD

RESET

PORT D

PD7:0

(8-bits) TIMER A

10-BIT ADC

PORT A

RAM

(384 - 1536Bytes)

PORT B

MCC/RTC/BEEP1

VAREF

VSSA

PORT E1

TIMER B1

PE5:0

(6-bits)

MTC VOLT INPUT

PA7:0 1)

(8-bits)

PORT F1

PF5:0

(6-bits)

SPI1

PB7:0

(8-bits)

VSS

WATCHDOG

OSC

LVD

OSC2

MEMORY

SCI/LIN

AVD

PWM ART

PORT C

(8-bits)

MOTOR CONTROL

PC7:0

PORT G 1)

PORT H 1)

PG7:0 1)

(8-bits)

PH7:0 1)

(8-bits)

MCES

On some devices only, see Table 1, “ST7MC Device Pin Description,” on page 12

DEBUG MODULE

PM ma)

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2 PIN DESCRIPTION

Figure 2. 80-Pin LQFP 14x14 Package Pinout

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PF0 / MCDEM / AIN8

VDD_0

VSS_0

VSSA

PD0 / OCMP2_A / AIN11

PH3

PH2

PH1

PF4 (HS)

PF1 / MCZEM / AIN9

PG1

PG2

PG3

OSC1

AIN2 / PA7

VDD_1

PG0

OSC2

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

(HS) MCO3

(HS) MCO4

(HS) MCO5

PG4

PG5

(HS) PC0

AIN5 / MCCFI 0/ PC1

MCPWMU/ PC5

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 /SS /(HS) PB7

OAP / PC2

OAN / PC3

AIN6 / MCCFI 1/ OAZ

MCPWMV/ PC6

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3 VPP/ICCSEL

PE5

PE4 / EXTCLK_B

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

RESET

PF3 (HS) / BEEP

PF5 (HS)

PH0

PG6

PG7

VAREF

PC7 / MCPWMW / AIN7

* MCCREF / PC4

PE3 / ICAP1_B

PH7

PH6

PH5

PE2 / ICAP2_B

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

PH4

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

VDD_2

VSS_2

PD4 /EXTCLK_A / AIN14 / ICCCLK

PF2 / MCO / AIN10

VSS_1

ei0

ei2

ei1

(HS) 20mA high sink capability

eix associated external interrupt vector

MCES

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

51 50 49 E]

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PIN DESCRIPTION (Cont’d)

Figure 3. 64-Pin LQFP 14x14 Package Pinout

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS /(HS) PB7

(HS) PC0

AIN5 / MCCFI0 / PC1

OAP / PC2

OAN / PC3

AIN6 / MCCFI1 / OAZ

* MCCREF / PC4

MCPWMU / PC5

MCPWMV/ PC6

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

ei2

ei0

ei1

VSS_1

VDD_1

OSC1

OSC2

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

PF5 (HS)

PF4 (HS)

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PE5 /

PE4 / EXTCLK_B

PE3 / ICAP1_B

PE2 / ICAP2_B

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

VDD_2

VSS_2

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

VPP /ICCSEL

(HS) 20mA high sink capability

eix associated external interrupt vector

ei1

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

jjjjjjjjjjjjjjjj u [K \j (\ CCCCCCCCCCCCCCEE

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PIN DESCRIPTION (Cont’d)

Figure 4. 32-Pin SDIP Package Pinouts

ICCSEL / VPP

MCO0

MCO1

MCO2

MCO3

MCO4

MCO5

MCES

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 / EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW / AIN11

RESET

VDD_0

VSS_0

VAREF

PC4 / MCCREF *

OAZ / MCCFI1 / AIN6

PC3 / OAN

PC2 / OAP

ei1

ei2

ei0

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

2j:2:Z:::::::::: < |\="" u="" )d="" \j="" z::eeeeeeeeeeqee:z:="">

ST7MC1xx/ST7MC2xx

9/309

PIN DESCRIPTION (Cont’d)

Figure 5. 56-Pin SDIP Package Pinouts

(HS) MCO1

(HS) MCO0

VPP/ICCSEL

ICAP1_B / PE3

ICAP2_B / PE2

OCMP1_B / PE1

MCES

(HS) MCO5

(HS) MCO4

(HS) MCO3

(HS) MCO2

OSC2

OSC1

Vdd_1

Vss_1

PWM2 / (HS) PA1

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS /(HS) PB7

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

PF3 (HS) / BEEP

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PE0 (HS) / OCMP2_B

VDD_2

VSS_2

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

OAZ / MCCFI1 / AIN6

PC4 / MCCREF *

PC3 / OAN

PC2 / OAP

PC6 / MCPWMV

PC5 / MCPWMU

PC1 / MCCFI0/AIN5

PC0(HS)

ei0

ei2

ei1

ei2

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

ST7MC1xx/ST7MC2xx

10/309

PIN DESCRIPTION (Cont’d)

Figure 6. 44-Pin LQFP Package Pinouts

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS /(HS) PB7

OAP / PC2

OAN / PC3

AIN6 / MCCFI1 / OAZ

* MCCREF / PC4

MCIA / PB1

MCIB / PB2

MCIC / PB3

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

ei2

ei0

ei1

VSS_1

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

PD0 / OCMP2_A / AIN11

RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV/MCDEM

PE3 / ICAP1_B

PE2 / ICAP2_B

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

VPP /ICCSEL

eix associated external interrupt vector

(HS) 20mA high sink capability

VDD_1

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

ST7MC1xx/ST7MC2xx

11/309

PIN DESCRIPTION (Cont’d)

Figure 7. 32-Pin LQFP 7x7 Package Pinout

MCIC / PB3

OAP / PC2

OAN / PC3

AIN6 / MCCFI1 / OAZ

* MCCREF / PC4

MCVREF / PB0

MCIA / PB1

MCIB / PB2

32 31 30 29 28 27 26 2524

9 10111213141516

8 ei1

ei0

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

RESET

VDD_0

VAREF

VSS_0

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW /AIN11

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

VPP /ICCSEL

ei2

eix associated external interrupt vector

(HS) 20mA high sink capability

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

ST7MC1xx/ST7MC2xx

12/309

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 247.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply

Input level: A = Dedicated analog input

In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger

TT= Refer to the G&H ports Characteristics in section 12.8.1 on page 264

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt 1), ana = analog

– Output: OD = open drain, PP = push-pull

Refer to “I/O PORTS” on page 54 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. ST7MC Device Pin Description

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function 2)

LQFP80

LQFP64

SDIP56

LQFP44

SDIP32

LQFP32

Input

Output

Input 1) Output

float

wpu

int

ana

118151MCO3 (HS) O HS XMotor Control Output 3

229262MCO4 (HS) O HS XMotor Control Output 4

3 3 10 3 7 3 MCO5 (HS) O HS X Motor Control Output 5

4411484MCES

3) IC

TXMTC Emergency Stop

5-----PG0 I/OT

TXXXXPort G0

6-----PG1 I/OT

TXXXXPort G1

7-----PG2 I/OT

TXXXXPort G2

8-----PG3 I/OT

TXXXXPort G3

9512595OSC1

4) IExternal clock input or Resonator

oscillator inverter input

106136106OSC2

4) I/O Resonator oscillator inverter output

117147 - -V

ss_15) S Digital Ground Voltage

128158 - -V

dd_15) S Digital Main Supply Voltage

13 9 - - - - PA0/PWM3 I/O CTXX X X Port A0 PWM Output 3

14 10 16 - - - PA1/PWM2 I/O CTHS XX X X Port A1 PWM Output 2

15 11 - - - - PA2PWM1 I/O CTXX X X Port A2 PWM Output 1

16 12 17 9 11 7 PA3/PWM0/

AIN0 I/O CTXei1 X X X Port A3 PWM Out-

put 0

ADC Ana-

log Input 0

17 13 18 - - - PA4 (HS)/ART-

CLK I/O CTHS XX X X Port A4 PWM-ART External Clock

18 14 19 10 12 8 PA5 / ARTIC1/

AIN1 I/O CTXei1 X X X Port A5

PWM-ART

Input Cap-

ture 1

ADC Analog

Input 1

19 15 20 - - - PA6 / ARTIC2 I/O CTXei1 X X Port A6 PWM-ART Input Capture

20 16 - - - - PA7/AIN2 I/O CTXei1 X X X Port A7 ADC Analog Input 2

ST7MC1xx/ST7MC2xx

13/309

21 17 21 11 13 9 PB0/MCVREF I/O CTXX X X X Port B0 MTC Voltage Reference

22 18 22 12 14 10 PB1/MCIA I/O CTXX X X X Port B1 MTC Input A

23 19 23 13 15 11 PB2/MCIB I/O CTXX X X X Port B2 MTC Input B

24 20 24 14 16 12 PB3/MCIC I/O CTXX X X X Port B3 MTC Input C

25 21 25 15 - - PB4/MISO I/O CTXXXXPort B4

SPI Master In / Slave Out

Data

26 22 26 16 - - PB5/MOSI/

AIN3 I/O CTXXXXPort B5

SPI Master

Out / Slave

In Data

ADC Ana-

log Input 3

27 23 27 17 - - PB6/SCK I/O CTHS Xei2 X X Port B6 SPI Serial Clock

28 24 28 18 - - PB7/SS/AIN4 I/O CTHS Xei2 X X Port B7

SPI Slave

Select (ac-

tive low)

ADC Ana-

log Input 4

29-----PG4 I/OT

TXXXXPort G4

30-----PG5 I/OT

TXXXXPort G5

31-----PG6 I/OT

TXXXXPort G6

32-----PG7 I/OT

TXXXXPort G7

33 25 29 - - - PC0 I/O CTHS Xei2 X X Port C0

34 26 30 - - - PC1/MCCFI06)

/AIN5 I/O CTXei2 X X X Port C1

MTC Cur-

rent Feed-

back Input

06)

ADC Ana-

log Input 5

35 27 31 19 17 13 PC2/OAP I/O CTXei2 X X X Port C2 OPAMP Positive Input

36 28 32 20 18 14 PC3/OAN I/O CTXX ei2 X X X Port C3 OPAMP Negative Input

37 29 33 21 19 15

OAZ/

MCCFI16)/

AIN6

I/O X Opamp

Output

MTC Cur-

rent Feed-

back Input

16)

ADC analog

Input 6

38 30 34 22 20 16 PC4/MCCREF I/O CTXXXXXPort C4

MTC Current Feedback

Reference 9)

39 31 35 - - - PC5/MCPW-

MU I/O CTXX X X Port C5 MTC PWM Output U

40 32 36 - - - PC6/

MCPWMV8) I/O CTXX X X Port C6 MTC PWM Output V8)

41 33 37 23 - -

PC7/

MCPWMW8)/

AIN7

I/O CTXXXXXPort C7

MTC PWM

Output W8)

ADC Ana-

log

Input 7

42 34 38 24 21 17 VAREF I Analog Reference Voltage for ADC

43 35 39 25 - - VSSA5) S Analog Ground Voltage

44 36 40 26 22 18 VSS_05) S Digital Ground Voltage

45 37 41 27 23 19 VDD_05) S Digital Main Supply Voltage

46 38 42 28 24 20 RESET I/O CTTop priority non maskable interrupt

Table 1. ST7MC Device Pin Description

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function 2)

LQFP80

LQFP64

SDIP56

LQFP44

SDIP32

LQFP32

Input

Output

Input 1) Output

float

wpu

int

ana

ST7MC1xx/ST7MC2xx

14/309

47 39 43 - - -

PF0/

MCDEM7)/

AIN8

I/O CTXXXXXPort F0

MTC De-

magnetiza-

tion

Output7)

ADC Ana-

log Input 8

48 40 44 - - - PF1/MCZEM7)/

AIN9 I/O CTXXXXXPort F1

MTC BEMF

Output7) ADC Ana-

log Input 9

49 41 - - - - PF2/MCO/

AIN10 I/O CTXXXXXPort F2

Main Clock

Out (fosc/2)

ADC Ana-

log Input 10

50 42 45 - - - PF3/BEEP I/O CTHS XX X X Port F3 Beep Signal Output

51 43 - - - - PF4 I/O CTHS XXXXPort F4

52 44 - - - - PF5 I/O CTHS XXXXPort F5

53-----PH0 I/OT

TXXXXPort H0

54-----PH1 I/OT

TXXXXPort H1

55-----PH2 I/OT

TXXXXPort H2

56-----PH3 I/OT

TXXXXPort H3

57 45 46 29 25 21

PD0/

OCMP2_A/

MCPWMW8)/

AIN11

I/O CTXXX XPort D0

Timer A Output Compare

MTC PWM Output W8)

ADC Analog Input 11

58 46 47 30 26 22

PD1 (HS)/

OCMP1_A/

MCPWMV8)/

MCDEM7)

I/O CTHS Xei0 X X Port D1

Timer A Output Compare

MTC PWM Output V8)

MTC Demagnetization7)

59 47 48 31 27 23

PD2/ICAP2_A/

MCZEM7) /

AIN12

I/O CTXei0 X X X Port D2

Timer A Input Capture 2

MTC BEMF7)

ADC Analog Input 12

60 48 49 32 28 24 PD3/ICAP1_A/

AIN13 I/O CTXei0 X X X Port D3

Timer A

Input

Capture 1

ADC

Analog

Input 13

61 49 50 33 29 25

PD4/

EXTCLK_A/IC-

CCLK/AIN14

I/O CTXei0 X X X Port D4

Timer A External Clock

source

ICC Clock Output

ADC Analog Input 14

62 50 51 34 30 26 PD5/ICCDA-

TA/AIN15 I/O CTXei0 X X X Port D5 ICC Data Input

ADC Analog Input 15

63 51 52 35 31 27 PD6/RDI I/O CTHS Xei0 X X Port D6 SCI Receive Data In

64 52 53 36 32 28 PD7/TDO I/O CTHS XX X X Port D7 SCI Transmit Data Output

65 53 54 - - - VSS_2 S Digital Ground Voltage

66 54 55 - - - VDD_2 S Digital Main Supply Voltage

67-----PH4 I/OT

TXXXXPort H4

68-----PH5 I/OT

TXXXXPort H5

Table 1. ST7MC Device Pin Description

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function 2)

LQFP80

LQFP64

SDIP56

LQFP44

SDIP32

LQFP32

Input

Output

Input 1) Output

float

wpu

int

ana

ST7MC1xx/ST7MC2xx

15/309

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,

else the configuration is floating interrupt input

2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV

and MCDEM on PD1 on LQFP32), the two signals will be ORed on the output pin.

3. MCES is a floating input. To disable this function, a pull-up resistor must be used.

4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla-

tor; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for

more details.

5. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA

pins to ground.

6. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:

- either to use PC1 as a standard I/O and map MCCFI on OAZ (MCCFI1) with or without using the oper-

ational amplifier (selected case after reset),

- or to map MCCFI on PC1 (MCCFI0) and use the amplifier for another function.

The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for

more details.

7. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.

MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.

8. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages.

MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package.

9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured

69-----PH6 I/OT

TXXXXPort H6

70-----PH7 I/OT

TXXXXPort H7

71 55 56 37 - - PE0/

OCMP2_B I/O CTHS XXXXPort E0

Timer B Output Compare

72 56 1 38 - - PE1/

OCMP1_B I/O CTXXXXXPort E1

Timer B Output Compare

73 57 2 39 - - PE2/ICAP2_B I/O CTXX X X Port E2 Timer B Input Capture 2

74 58 3 40 - - PE3/ICAP1_B/ I/O CTXX X X X Port E3 Timer B Input Capture 1

75 59 - - - - PE4/

EXTCLK_B I/O CTXXXXPort E4

Timer B External Clock

source

76 60 - - - - PE5 I/O CTXXXXXPort E5

77 61 4 41 1 29 VPP/ICCSEL I

Must be tied low. In the program-

ming mode when available, this pin

acts as the programming voltage in-

put VPP./ ICC mode pin. See section

12.9.2 on page 269

78 62 5 42 2 30 MCO0 (HS) O HS X MTC Output Channel 0

79 63 6 43 3 31 MCO1 (HS) O HS X MTC Output Channel 1

80 64 7 44 4 32 MCO2 (HS) O HS X MTC Output Channel 2

Table 1. ST7MC Device Pin Description

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function 2)

LQFP80

LQFP64

SDIP56

LQFP44

SDIP32

LQFP32

Input

Output

Input 1) Output

float

wpu

int

ana

ST7MC1xx/ST7MC2xx

16/309

to an alternate function. PC4 is no longer usable as a digital I/O.l

10. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up

configuration after reset. The configuration of these pads must be kept at reset state to avoid added cur-

rent consumption. Refer to section 15.7 on page 303

ST7MC1xx/ST7MC2xx

17/309

3 REGISTER & MEMORY MAP

As shown in Figure 8, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128

bytes of register locations, up to 2Kbytes of RAM

and up to 60Kbytes of user program memory. The

RAM space includes up to 256 bytes for the stack

from 0100h to 01FFh.

The highest address bytes contain the user reset

and interrupt vectors.

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

served area can have unpredictable effects on the

device.

Figure 8. Memory Map

As shown in Figure 9, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128

bytes of register locations, up to 1536 bytes of

RAM and up to 60 Kbytes of user program memo-

ry. The RAM space includes up to 256 bytes for

the stack from 0100h to 01FFh.

The highest address bytes contain the user reset

and interrupt vectors.

0000h

RAM

Program Memory

(60K, 48K, 32K, 16K, 8K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

FFDFh

FFE0h

FFFFh (see Table 8)

0680h Reserved

067Fh

Short Addressing

RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

0080h

0200h

00FFh

1000h

32 KBytes

60 KBytes

FFFFh

8000h

(1536/1024

or 047Fh

8 KBytes

E000h

768/384 Bytes)

or 037Fh

or 067Fh

16 KBytes

C000h

48 KBytes

4000h

ST7MC1xx/ST7MC2xx

18/309

Table 2. Hardware Register Map

Address Block Register

Label Register Name Reset

Status Remarks

0000h

0001h

0002h

Port A

PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h1)

00h

R/W

R/W2)

0003h

0004h

0005h

Port B

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h1)

00h

R/W

0006h

0007h

0008h

Port C

PCDR

PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

00h1)

00h

R/W

0009h

000Ah

000Bh

Port D

PDDR

PDDDR

PDOR

Port D Data Register

Port D Data Direction Register

Port D Option Register

00h1)

00h

R/W

000Ch

000Dh

000Eh

Port E

PEDR

PEDDR

PEOR

Port E Data Register

Port E Data Direction Register

Port E Option Register

00h1)

00h

R/W

R/W2)

000Fh

0010h

0011h

Port F

PFDR

PFDDR

PFOR

Port F Data Register

Port F Data Direction Register

Port F Option Register

00h1)

00h

R/W

0012h

0013h

0014h

Port G

PGDR

PGDDR

PGOR

Port G Data Register

Port G Data Direction Register

Port G Option Register

00h1)

00h

R/W

0015h

0016h

0017h

Port H

PHDR

PHDDR

PHOR

Port H Data Register

Port H Data Direction Register

Port H Option Register

00h1)

00h

R/W

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

LINSCI™

SCISR

SCIDR

SCIBRR

SCICR1

SCICR2

SCICR3

SCIERPR

SCIETPR

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

SCI Control Register 3

SCI Extended Receive Prescaler Register

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

xxh

00h

Read Only

R/W

0020h Reserved Area (1 Byte)

0021h

0022h

0023h

SPI

SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Control/Status Register

xxh

0xh

00h

R/W

ST7MC1xx/ST7MC2xx

19/309

0024h

0025h

0026h

0027h

0028h

ITC

ITSPR0

ITSPR1

ITSPR2

ITSPR3

EICR

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

External Interrupt Control Register

FFh

00h

R/W

0029h FLASH FSCR Flash Control/Status Register 00h R/W

002Ah

002Bh WATCHDOG

WDGCR Window Watchdog Control Register 7Fh R/W

WDGWR Window Watchdog Window Register 7Fh R/W

002Ch

002Dh MCC MCCSR

MCCBCR

Main Clock Control / Status Register

Main Clock Controller: Beep Control Register

00h

R/W

002Eh

002Fh

0030h

ADC

ADCCSR

ADCDRMSB

ADCDRLSB

Control/Status Register

Data Register MSB

Data Register LSB

00h

R/W

Read Only

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TIMER A

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

TACLR

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

Timer A Counter Low Register

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

Read Only

R/W

0040h SIM SICSR System Integrity Control/Status Register 000x000x b R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TIMER B

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

TBCLR

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

Timer B Counter Low Register

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

Read Only

R/W

Table 2. Hardware Register Map

Address Block Register

Label Register Name Reset

Status Remarks

ST7MC1xx/ST7MC2xx

20/309

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

MTC

(page 0)

MTIM

MTIML

MZPRV

MZREG

MCOMP

MDREG

MWGHT

MPRSR

MIMR

MISR

MCRA

MCRB

MCRC

MPHST

MDFR

MCFR

MREF

MPCR

MREP

MCPWH

MCPWL

MCPVH

MCPVL

MCPUH

MCPUL

MCP0H

MCP0L

Timer Counter High Register

Timer Counter Low Register

Capture Zn-1 Register

Capture Zn Register

Compare Cn+1 Register

Demagnetization Register

An Weight Register

Prescaler & Sampling Register

Interrupt Mask Register

Interrupt Status Register

Control Register A

Control Register B

Control Register C

Phase State Register

D event Filter Register

Current feedback Filter Register

Reference Register

PWM Control Register

Repetition Counter Register

Compare Phase W Preload Register High

Compare Phase W Preload Register Low

Compare Phase V Preload Register High

Compare Phase V Preload Register Low

Compare Phase U Preload Register High

Compare Phase U Preload Register Low

Compare Phase 0 Preload Register High

Compare Phase 0 Preload Register Low

00h

0Fh

00h

0Fh

FFh

R/W

0050h

0051h

0052h

0053h

0054h

0055h

0056h

MTC

(page 1)

MDTG

MPOL

MPWME

MCONF

MPAR

MZRF

MSCR

Dead Time Generator Enable

Polarity Register

PWM Register

Configuration Register

Parity Register

Z event Filter Register

Sampling Clock Register

FFh

3Fh

00h

02h

00h

0Fh

00h

see MTC

description

0057h to

006Ah Reserved Area (4 Bytes)

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

Debug Control Register

Debug Status Register

Debug Breakpoint 1 MSB Register

Debug Breakpoint 1 LSB Register

Debug Breakpoint 2 MSB Register

Debug Breakpoint 2 LSB Register

00h

10h

FFh

R/W

Read Only

R/W

Table 2. Hardware Register Map

Address Block Register

Label Register Name Reset

Status Remarks

ST7MC1xx/ST7MC2xx

21/309

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

PWM ART

PWMDCR3

PWMDCR2

PWMDCR1

PWMDCR0

PWMCR

ARTCSR

ARTCAR

ARTARR

ARTICCSR

ARTICR1

ARTICR2

PWM AR Timer Duty Cycle Register 3

PWM AR Timer Duty Cycle Register 2

PWM AR Timer Duty Cycle Register 1

PWM AR Timer Duty Cycle Register 0

PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register

Auto-Reload Timer Counter Access Register

Auto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg.

AR Timer Input Capture Register 1

AR Timer Input Capture Register 2

00h

R/W

Read Only

007Fh OPAMP OACSR OPAMP Control/Status Register 00h R/W

Table 2. Hardware Register Map

Address Block Register

Label Register Name Reset

Status Remarks

@ﬁGﬂGGQQ H

ST7MC1xx/ST7MC2xx

22/309

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be

electrically erased as a single block or by individu-

al sectors and programmed on a Byte-by-Byte ba-

sis using an external VPP supply.

The HDFlash devices can be programmed and

erased off-board (plugged in a programming tool)

or on-board using ICP (In-Circuit Programming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

4.2 MAIN FEATURES

■3 Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

■ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■Read-out protection

■Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 STRUCTURE

The Flash memory is organised in sectors and can

be used for both code and data storage.

Depending on the overall Flash memory size in the

microcontroller device, there are up to three user

sectors (see Table 3). Each of these sectors can

be erased independently to avoid unnecessary

erasing of the whole Flash memory when only a

partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes

(see Figure 9). They are mapped in the upper part

of the ST7 addressing space so the reset and in-

terrupt vectors are located in Sector 0 (F000h-

FFFFh).

Table 3. Sectors available in Flash devices

4.3.1 Read-out Protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry. Even if no protection can be considered as to-

tally unbreakable, the feature provides a very high

level of protection for a general purpose microcon-

troller.

In Flash devices, this protection is removed by re-

programming the option. In this case, the entire

program memory is first automatically erased and

the device can be reprogrammed.

Read-out protection selection depends on the de-

vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 9. Memory Map and Sector Address

Flash Size (bytes) Available Sectors

4K Sector 0

8K Sectors 0,1

> 8K Sectors 0,1, 2

4 Kbytes

2Kbytes

SECTOR 1

SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8 Kbytes 40 Kbytes 52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

'11::3'1ﬂ—f DEEDS HEDGE C sessio a

ST7MC1xx/ST7MC2xx

23/309

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC INTERFACE

ICC (In-Circuit Communication) needs a minimum

of four and up to six pins to be connected to the

programming tool (see Figure 10). These pins are:

– RESET: device reset

–V

SS: device power supply ground

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

– ICCSEL/VPP: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

–V

DD: application board power supply (see Fig-

ure 10, Note 3)

Figure 10. Typical ICC Interface

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

2. During the ICC session, the programming tool

must control the RESET pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

classical RC network with R > 1K or a reset man-

agement IC with open drain output and pull-up

resistor > 1K, no additional components are need-

ed. In all cases the user must ensure that no exter-

nal reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS-

CIN pin of the ST7 when the clock is not available

in the application or if the selected clock option is

not programmed in the option byte. ST7 devices

with multi-oscillator capability need to have OSC2

grounded in this case.

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTOR TYPE

APPLICATION

POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

VSS

ICCSEL/VPP

ST7

CL2 CL1

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION

RESET SOURCE

APPLICATION

I/O

(See Note 4)

ST7MC1xx/ST7MC2xx

24/309

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (IN-CIRCUIT PROGRAMMING)

To perform ICP the microcontroller must be

switched to ICC (In-Circuit Communication) mode

by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully custom-

ized (number of bytes to program, program loca-

tions, or selection serial communication interface

for downloading).

When using an STMicroelectronics or third-party

programming tool that supports ICP and the spe-

cific microcontroller device, the user needs only to

implement the ICP hardware interface on the ap-

plication board (see Figure 10). For more details

on the pin locations, refer to the device pinout de-

scription.

4.6 IAP (IN-APPLICATION PROGRAMMING)

This mode uses a BootLoader program previously

stored in Sector 0 by the user (in ICP mode or by

plugging the device in a programming tool).

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI or

other type of serial interface and program it in the

Flash. IAP mode can be used to program any of

the Flash sectors except Sector 0, which is write/

erase protected to allow recovery in case errors

occur during the programming operation.

4.7 RELATED DOCUMENTATION

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual.

4.8 REGISTER DESCRIPTION

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

This register is reserved for use by Programming

Tool software. It controls the Flash programming

and erasing operations.

00000000

ST7MC1xx/ST7MC2xx

25/309

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect

addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power Halt and Wait modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The six CPU registers shown in Figure 11 are not

present in the memory mapping and are accessed

by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

Index Registers (X and Y)

These 8-bit registers are used to create effective

addresses or as temporary storage areas for data

manipulation. (The Cross-Assembler generates a

precede instruction (PRE) to indicate that the fol-

lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto-

matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 11. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH PCL

15 870

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE = 1X11X1XX

RESET VALUE = XXh

X = Undefined Value

ST7MC1xx/ST7MC2xx

26/309

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-

terrupt masks and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

These bits can be individually tested and/or con-

trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instructions. It is reset by hardware during

the same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It’s a copy of the re-

sult 7th bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (IxSPR). They can be also set/

cleared by software with the RIM, SIM, IRET,

HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more

details.

11I1HI0NZ

Interrupt Software Priority I1 I0

Level 0 (main) 1 0

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

ST7MC1xx/ST7MC2xx

27/309

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 12).

Since the stack is 256 bytes deep, the 8 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP7 to SP0 bits are set) which is the stack

higher address.

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 12.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 12. Stack Manipulation Example

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

CALL

Subroutine Interrupt

Event

PUSH Y POP Y IRET RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

ST7MC1xx/ST7MC2xx

28/309

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 13.

For more details, refer to dedicated parametric

section.

Main features

■Reset Sequence Manager (RSM)

■1 Crystal/Ceramic resonator oscillator

■System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

– Clock Security System (CSS) with the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector

– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is

8MHz

Figure 13. Clock, Reset and Supply Block Diagram

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

OSCILLATOR

OSC1

RESET

VSS

VDD

RESET SEQUENCE

MANAGER

(RSM)

CLOCK SECURITY SYSTEM

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

SYSTEM

WATCHDOG

SICSR, page 0 TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD LVD

CSS

WDG

fOSC

fCPU

fMTC

1/2

Safeosc

8Mhz PLL

Clock Detector

VCO CK 0

PA LO

PLL

SICSR, page 1

16Mhz

fOSC

CKSEL

DIV2 OPT

lock

GE 00

INTEGRITY MANAGEMENT

SEL

fCLK

* It is recommended to decouple the power supply by placing a 0.1µF capacitor as close as possible to VDD

ST7MC1xx/ST7MC2xx

29/309

6.1 OSCILLATOR

The main clock of the ST7 can be generated by a

crystal or ceramic resonator oscillator or an exter-

nal source.

The associated hardware configurations are

shown in Table 4. Refer to the electrical character-

istics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,

sinus or triangle) with ~50% duty cycle has to drive

the OSC1 pin while the OSC2 pin is not connect-

ed.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-

ducing a very accurate rate on the main clock of

the ST7. In this mode, the resonator and the load

capacitors have to be placed as close as possible

to the oscillator pins in order to minimize output

distortion and start-up stabilization time.

This oscillator is not stopped during the RESET

phase to avoid losing time in its start-up phase.

See Electrical Characteristics for more details.

Note: When crystal oscillator is used as a clock

source, a risk of failure may exist if no series resis-

tors are implemented.

Table 4. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic Resonators

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

CL2

CL1

1F T77

ST7MC1xx/ST7MC2xx

30/309

6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 15:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 11.2.1 on page 244 for further de-

tails.

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 14:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (selected by

option byte)

■RESET vector fetch

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector

is not programmed. For this reason, it is recom-

mended to keep the RESET pin in low state until

programming mode is entered, in order to avoid

unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay should be selected by

option byte to correspond to the stabilization time

of the external oscillator used in the application.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 14. RESET Sequence Phases

6.2.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in

order to be recognized (see Figure 16). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in Halt mode.

Figure 15. Reset Block Diagram

RESET

Active Phase INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

Filter

ILLEGAL OPCODE RESET 1)

Note 1: See “Illegal Opcode Reset” on page 244. for more details on illegal opcode reset conditions.

ded by a g Irom m ASE E]

ST7MC1xx/ST7MC2xx

31/309

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

6.2.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until VDD is over the minimum

level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

6.2.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 16.

The LVD filters spikes on VDD larger than tg(VDD) to

avoid parasitic resets.

6.2.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 16. RESET Sequences

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

RUN

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN RUN

RESET

SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE

PHASE

ST7MC1xx/ST7MC2xx

32/309

6.3 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains

the Low Voltage Detector (LVD), Auxiliary Voltage

Detector (AVD) and Clock Security System (CSS)

functions. It is managed by the SICSR register.

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re-

fer to section 11.2.1 on page 244 for further de-

tails.

6.3.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) gener-

ates a static reset when the VDD supply voltage is

below a VIT- reference value. This means that it

secures the power-up as well as the power-down

keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower

than the VIT+ reference value for power-on in order

to avoid a parasitic reset when the MCU starts run-

ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

VDD is below:

–V

IT+ when VDD is rising

–V

IT- when VDD is falling

The LVD function is illustrated in Figure 17.

Provided the minimum VDD value (guaranteed for

the oscillator frequency) is above VIT-, the MCU

can only be in two modes:

– under full software control

– in static safe reset

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

Notes:

The LVD allows the device to be used without any

external RESET circuitry.

The LVD is an optional function which can be se-

lected by option byte.

It is recommended to make sure that the VDD sup-

ply voltage rises monotonously when the device is

exiting from Reset, to ensure the application func-

tions properly.

Figure 17. Low Voltage Detector vs Reset

VDD

VIT+

RESET

VIT-

Vhys

ST7MC1xx/ST7MC2xx

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on

an analog comparison between a VIT-(AVD) and

VIT+(AVD) reference value and the VDD main sup-

ply. The VIT- reference value for falling voltage is

lower than the VIT+ reference value for rising volt-

age in order to avoid parasitic detection (hystere-

sis).

The output of the AVD comparator is directly read-

able by the application software through a real-

time status bit (AVDF) in the SICSR register. This

bit is read only.

Caution: The AVD function is active only if the

LVD is enabled through the option byte (see sec-

tion 14.1 on page 290).

6.3.2.1 Monitoring the VDD Main Supply

If the AVD interrupt is enabled, an interrupt is gen-

erated when the voltage crosses the VIT+(AVD) or

VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt

acts as an early warning, allowing software to shut

down safely before the LVD resets the microcon-

troller. See Figure 18.

The interrupt on the rising edge is used to inform

the application that the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096

CPU cycles (depending on the reset delay select-

ed by option byte), no AVD interrupt will be gener-

ated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

VIT+(AVD) threshold is reached, then 2 AVD inter-

rupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is

reached.

– If the AVD interrupt is enabled after the VIT+(AVD)

threshold is reached then only one AVD interrupt

will occur.

Figure 18. Using the AVD to Monitor VDD

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit 0 01

IF AVDIE bit = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT PROCESS INTERRUPT PROCESS

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

trv VOLTAGE RISE TIME

ST7MC1xx/ST7MC2xx

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a PLL which can provide a

backup clock. The PLL can be enabled or disabled

by option byte or by software. It requires an 8-MHz

input clock and provides a 16-MHz output clock.

6.3.3.1 Safe Oscillator Control

The safe oscillator of the CSS block is made of a

PLL.

If the clock signal disappears (due to a broken or

disconnected resonator...) the PLL continues to

provide a lower frequency, which allows the ST7 to

perform some rescue operations.

Note: The clock signal must be present at start-up.

Otherwise, the ST7MC will not start and will be

maintained in RESET conditions.

6.3.3.2 Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the SICSR

SIE bit has been previously set.

These two bits are described in the SICSR register

description.

6.3.4 Low Power Modes

6.3.4.1 Interrupts

The CSS or AVD interrupt events generate an in-

terrupt if the corresponding Enable Control Bit

(CSSIE or AVDIE) is set and the interrupt mask in

the CC register is reset (RIM instruction).

Note 1: This interrupt allows to exit from Active-

halt mode.

Mode Description

Wait No effect on SI. CSS and AVD interrupts

cause the device to exit from Wait mode.

Halt

The CRSR register is frozen.

The CSS (including the safe oscillator) is

disabled until Halt mode is exited. The pre-

vious CSS configuration resumes when the

MCU is woken up by an interrupt with “exit

from Halt mode” capability or from the coun-

ter reset value when the MCU is woken up

by a RESET. The AVD remains active, and

an AVD interrupt can be used to exit from

Halt mode.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

CSS event detection

(safe oscillator acti-

vated as main clock)

CSSD CSSIE Yes No 1)

AVD event AVDF AVDIE Yes Yes

ST7MC1xx/ST7MC2xx

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0)

Read/Write

Reset Value: 000x 000x (00h)

Bit 7 = PAGE SICSR Register Page Selection

This bit selects the SICSR register page. It is set

and cleared by software

0: Access to SICSR register mapped in page 0.

1: Access to SICSR register mapped in page 1.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the VDIE bit is set, an interrupt request is gener-

ated when the AVDF bit changes value.

0: VDD over VIT+ (AVD) threshold

1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance

is detected by the Clock Security System (CSSD

bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the PLL is disabled (PLLEN=0), the CSSIE

bit has no effect.

Bit 1 = CSSD Clock security system detection

This bit indicates a disturbance on the main clock

signal (fOSC): the clock stops (at least for a few cy-

cles). It is set by hardware and cleared by reading

the SICSR register when the original oscillator re-

covers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the PLL is disabled (PLLEN=0), the CSSD

bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

PAG

AVD

LVD

RF 0CSS

CSS

WDG

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

ST7MC1xx/ST7MC2xx

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1)

Reset Value: 00000000 (00h)

Bit 7 = PAGE SICSR Register Page Selection

This bit selects the SICSR register page. It is set

and cleared by software

0: Access to SICSR register mapped in page 0.

1: Access to SICSR register mapped in page 1.

Bit 6 = Reserved, must be kept cleared.

Bit 5 = VCOEN VCO Enable

This bit is set and cleared by software.

0: VCO (Voltage Controlled Oscillator) connected

to the output of the PLL charge pump (default

mode), to obtain a 16-MHz output frequency

(with an 8-MHz input frequency).

1: VCO tied to ground in order to obtain a 10-MHz

frequency (fvco)

Notes:

1. During ICC session, this bit is set to 1 in order to

have an internal frequency which does not depend

on the input clock. Then, it can be reset in order to

run faster with an external oscillator.

Bit 4 = LOCK PLL Locked

This bit is read only. It is set by hardware. It is set

automatically when the PLL reaches its operating

frequency.

0: PLL not locked

1: PLL locked

Bit 3 = PLLEN PLL Enable

This bit enables the PLL and the clock detector. It

is set and cleared by software.

0: PLL and Clock Detector (CKD) disabled

1: PLL and Clock Detector (CKD) enabled

Notes:

1. During ICC session, this bit is set to 1.

2. PLL cannot be disabled if PLL clock source is

selected (CKSEL= 1).

Bit 2 = Reserved, must be kept cleared.

Bit 1 = CKSEL Clock Source Selection

This bit selects the clock source: oscillator clock or

clock from the PLL. It is set and cleared by soft-

ware. It can also be set by option byte (PLL opt)

0: Oscillator clock selected

1: PLL clock selected

Notes:

1. During ICC session, this bit is set to 1. Then,

CKSEL can be reset in order to run with fOSC.

2. Clock from the PLL cannot be selected if the

PLL is disabled (PLLEN =0)

3. If the clock source is selected by PLL option bit,

CKSEL bit selection has no effect.

Bit 0 = Reserved, must be kept cleared.

GE 0VCO

PLL

EN 0CK-

SEL 0

ST7MC1xx/ST7MC2xx

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6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-

ent functions:

■a programmable CPU clock prescaler

■a clock-out signal to supply external devices

■a real-time clock timer with interrupt capability

Each function can be used independently and si-

multaneously.

6.4.1 Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies

the clock for the ST7 CPU and its internal periph-

erals. It manages Slow power saving mode (See

Section 8.2 SLOW MODE for more details).

The prescaler selects the fCPU main clock frequen-

cy and is controlled by three bits in the MCCSR

6.4.2 Clock-out Capability

The clock-out capability is an alternate function of

an I/O port pin that outputs a fOSC2 clock to drive

external devices. It is controlled by the MCO bit in

the MCCSR register.

CAUTION: When selected, the clock out pin sus-

pends the clock during Active-halt mode.

6.4.3 Real-time Clock Timer (RTC)

The counter of the real-time clock timer allows an

interrupt to be generated based on an accurate

real-time clock. Four different time bases depend-

ing directly on fOSC2 are available. The whole

functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters Active-halt mode when the HALT

instruction is executed. See Section 8.4 ACTIVE-

HALT AND HALT MODES for more details.

6.4.4 Beeper

The beep function is controlled by the MCCBCR

on the BEEP pin (I/O port alternate function).

Figure 19. Main Clock Controller (MCC/RTC) Block Diagram

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMS

DIV128

CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

RTC

COUNTER

TO CPU AND

PERIPHERALS

fOSC2

fCPU

MCO

BC1 BC0

MCCBCR

BEEP

GENERATOR

BEEP SIGNAL

TO MOTOR

CONTROL

PERIPHERAL

fMTC

(AND TO MTC

PERIPHERAL)

DIV 2, 4, 8, 16

DIV 2

fCLK

DIV 2 fADC

ST7MC1xx/ST7MC2xx

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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)

6.4.5 Low Power Modes

6.4.6 Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

Note:

The MCC/RTC interrupt wakes up the MCU from

Active-halt mode, not from Halt mode.

6.4.7 Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (fOSC2on I/O

port)

Note: To reduce power consumption, the MCO

function is not active in Active-halt mode.

Bit 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 8.2 SLOW MODE and Section 6.4

MAIN CLOCK CONTROLLER WITH REAL-TIME

CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time

base. They are set and cleared by software.

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real-time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from Active-halt

mode.

When this bit is set, calling the ST7 software HALT

instruction enters the Active-halt power saving

mode.

Mode Description

Wait

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from Wait mode.

Active-

halt

No effect on MCC/RTC counter (OIE bit is

set), the registers are frozen.

MCC/RTC interrupt cause the device to exit

from Active-halt mode.

Halt

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from Halt” capability.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow

event OIF OIE Yes No 1)

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

fCPU in Slow mode CP1 CP0

fOSC2 / 2 0 0

fOSC2 / 4 0 1

fOSC2 / 8 1 0

fOSC2 / 16 1 1

Counter

Prescaler

Time Base

TB1 TB0

fOSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

ST7MC1xx/ST7MC2xx

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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved, must be kept cleared.

Bit 3 = ADSTS A/D Converter Sample Time

Stretch

This bit is set and cleared by software to enable or

disable the A/D Converter sample time stretch fea-

ture.

0: AD sample time stretch disabled (for standard

impedance analog inputs)

1 AD sample time stretch enabled (for high imped-

ance analog inputs)

Bit 2 = ADCIE A/D Converter Interrupt Enable

This bit is set and cleared by software to enable or

disable the A/D Converter interrupt.

0: AD Interrupt disabled

1 AD Interrupt enabled

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in Active-halt

mode but has to be disabled to reduce the con-

sumption.

Table 5. Main Clock Controller Register Map and Reset Values

0000

AD-

STS

ADC

IE BC1 BC0

BC1 BC0 Beep mode with fOSC2=8MHz

00 Off

01 ~2-KHz Output

Beep signal

~50% duty cycle

10 ~1-KHz

1 1 ~500-Hz

Address

(Hex.)

Label 76543210

0040h SICSR, page0

Reset Value

PAGE

VDIE

VDF

LVDRF

CFIE

CSSD

WDGRF

0040h SICSR, page1

Reset Value

PAGE

VCOEN

LOCK

PLLEN

CKSEL

002Ch MCCSR

Reset Value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh MCCBCR

Reset Value0000

ADSTS

ADCIE

BC1

BC0

ST7MC1xx/ST7MC2xx

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro-

vides the following features:

■Hardware interrupts

■Software interrupt (TRAP)

■Nested or concurrent interrupt management

with flexible interrupt priority and level

management:

– Up to 4 software programmable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP

– 1 maskable top level event: MCES

This interrupt management is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

each interrupt vector (see Table 6). The process-

ing flow is shown in Figure 20

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers

of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Figure 20. Interrupt Processing Flowchart

Interrupt software priority Level I1 I0

Level 0 (main) Low

High

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET MCES

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

5] he \merr enas

ST7MC1xx/ST7MC2xx

41/309

INTERRUPTS (Cont’d)

Servicing Pending Interrupts

As several interrupts can be pending at the same

time, the interrupt to be taken into account is deter-

mined by the following two-step process:

– the highest software priority interrupt is serviced,

– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware

priority is serviced first.

Figure 21 describes this decision process.

Figure 21. Priority Decision Process

When an interrupt request is not serviced immedi-

ately, it is latched and then processed when its

software priority combined with the hardware pri-

ority becomes the highest one.

Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous

process to succeed with only one interrupt.

Note 2: RESET, TRAP and MCES can be consid-

ered as having the highest software priority in the

decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the

ST7 interrupt controller: the non-maskable type

(RESET, TRAP) and the maskable type (external

or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the

state of the I1 and I0 bits of the CC register (see

Figure 20). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit Halt

mode.

■TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP

instruction is executed. It will be serviced accord-

ing to the flowchart in Figure 20 as a MCES top

level interrupt.

■RESET

The RESET source has the highest priority in the

ST7. This means that the first current routine has

the highest software priority (level 3) and the high-

est hardware priority.

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced

if the corresponding interrupt is enabled and if its

own interrupt software priority (in ISPRx registers)

is higher than the one currently being serviced (I1

and I0 in CC register). If any of these two condi-

tions is false, the interrupt is latched and thus re-

mains pending.

■MCES (MTC Emergency Stop)

This hardware interrupt occurs when a specific

edge is detected on the dedicated MCES pin or

when an error is detected by the micro in the motor

speed measurement. The interrupt request is

maintained as long as the MCES pin is low if the

interrupt is enabled by the EIM bit in the MIMR reg-

ister.

■External Interrupts

External interrupts allow the processor to exit from

Halt low power mode.

External interrupt sensitivity is software selectable

through the External Interrupt Control register

(EICR).

External interrupt triggered on edge will be latched

and the interrupt request automatically cleared

upon entering the interrupt service routine.

If several input pins of a group connected to the

same interrupt line are selected simultaneously,

these will be logically ORed.

■Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to

exit from Halt mode except those mentioned in the

“Interrupt Mapping” table.

A peripheral interrupt occurs when a specific flag

is set in the peripheral status registers and if the

corresponding enable bit is set in the peripheral

control register.

The general sequence for clearing an interrupt is

based on an access to the status register followed

by a read or write to an associated register.

Note: The clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being

serviced) will therefore be lost if the clear se-

quence is executed.

PENDING

SOFTWARE Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

ST7MC1xx/ST7MC2xx

42/309

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the Wait

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the Halt modes (see column “Exit from

Halt” in “Interrupt Mapping” table). When several

pending interrupts are present while exiting Halt

mode, the first one serviced can only be an inter-

rupt with exit from Halt mode capability and it is se-

lected through the same decision process shown

in Figure 21.

Note: If an interrupt, that is not able to Exit from

Halt mode, is pending with the highest priority

when exiting Halt mode, this interrupt is serviced

after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 22 and Figure 23 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 23. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, MCES. The software priority

is given for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

Figure 22. Concurrent Interrupt Management

Figure 23. Nested Interrupt Management

MAIN

IT4

IT2

IT1

MCES

IT1

MAIN

IT0

HARDWARE PRIORITY

SOFTWARE

3/0

11 / 10

RIM

IT2

IT1

IT4

MCES

IT3

IT0

IT3

PRIORITY

LEVEL

USED STACK = 10 BYTES

MAIN

IT2

MCES

MAIN

IT0

IT2

IT1

IT4

MCES

IT3

IT0

HARDWARE PRIORITY

3/0

RIM

IT1

IT4 IT4

IT1

IT2

IT3

I1 I0

11 / 10 10

SOFTWARE

PRIORITY

LEVEL

USED STACK = 20 BYTES

ST7MC1xx/ST7MC2xx

43/309

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read/Write

Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt soft-

ware priority.

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (ISPRx).

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

*Note: MCES, TRAP and RESET events can in-

terrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

These four registers contain the interrupt software

priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondence is shown in the following table.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The RESET, TRAP and MCES vectors have no

software priorities. When one is serviced, the I1

and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre-

spond to the MCES can be read and written but

they are not significant in the interrupt process

management.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

11I1 HI0 NZC

Interrupt Software Priority Level I1 I0

Level 0 (main) Low

High

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable*) 1 1

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

ST7MC1xx/ST7MC2xx

44/309

INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

Table 8. Interrupt Mapping

Note 1. Valid for Halt and Active-halt modes except for the MCC/RTC or CSS interrupt source which exits from Active-

halt mode only.

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0=11 (level 3) I1:0=11 ?

JRNM Jump if I1:0<>11 I1:0<>11 ?

POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

N° Source

Block Description Register

Label

Priority

Order

Exit

from

Halt1)

Address

Vector

RESET Reset N/A

Highest

Priority

Lowest

Priority

yes FFFEh-FFFFh

TRAP Software interrupt no FFFCh-FFFDh

0MCES

Motor Control Emergency Stop

or Speed error interrupt

MISR

MCRC no FFFAh-FFFBh

1MCC/RTC

CSS

Main clock controller time base interrupt

Safe oscillator activation interrupt

MCCSR

SICSR yes FFF8h-FFF9h

2 ei0 External interrupt port

N/A

yes FFF6h-FFF7h

3 ei1 External interrupt port yes FFF4h-FFF5h

4 ei2 External interrupt port yes FFF2h-FFF3h

MTC

Event U or Current Loop or Sampling Out MISR/MCONF no FFF0h-FFF1h

6 Event R or Event Z MISR no FFEEh-FFEFh

7 Event C or Event D no FFECh-FFEDh

8 SPI SPI peripheral interrupts SPICSR yes FFEAh-FFEBh

9 TIMER A TIMER A peripheral interrupts TASR no FFE8h-FFE9h

10 TIMER B TIMER B peripheral interrupts TBSR no FFE6h-FFE7h

11 LINSCI™LINSCI™ Peripheral interrupts SCISR no FFE4h-FFE5h

12 AVD/

ADC

Auxiliary Voltage detector interrupt

ADC End of conversion interrupt

SICSR

ADCSR yes FFE2h-FFE3h

13 PWM ART PWM ART overflow interrupt

PWM ART input capture interrupts

ARTCSR

ARTICCSR no FFE0h-FFE1h

ST7MC1xx/ST7MC2xx

45/309

INTERRUPTS (Cont’d)

7.6 EXTERNAL INTERRUPTS

The pending interrupts are cleared writing a differ-

ent value in the ISx[1:0], IPA or IPB bits of the

EICR.

Note: External interrupts are masked when an I/O

(configured as input interrupt) of the same inter-

rupt vector is forced to VSS.

7.6.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 24). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated

on four (or five) different events on the pin:

■Falling edge

■Rising edge

■Falling and rising edge

■Falling edge and low level

■Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3).

ST7MC1xx/ST7MC2xx

46/309

INTERRUPTS (Cont’d)

Figure 24. External Interrupt Control bits

IS20 IS21

EICR

SENSITIVITY

CONTROL

PAOR.7

PADDR.7

PA7 ei1 INTERRUPT SOURCE

PORT A3, PORT A[7:5] INTERRUPTS

PA7

PA6

PA5

PA3

IS10 IS11

EICR

SENSITIVITY

CONTROL

PCOR.0

PCDDR.0

PC0 ei2 INTERRUPT SOURCE

PORT C0, PORT B[7:6] INTERRUPTS

PC0

PB7

PB6

IS30 IS31

EICR

SENSITIVITY

CONTROL

PDOR.6

PDDDR.6

IPA BIT

PD6 ei0 INTERRUPT SOURCE

PORT D [6:4] INTERRUPTS

PD6

PD5

PD4

IS30 IS31

EICR

SENSITIVITY

CONTROL

PDOR.3

PDDDR.3

PD3 ei0 INTERRUPT SOURCE

PORT D [3:1] INTERRUPTS

PD3

PD2

PD1

IS10 IS11

EICR

SENSITIVITY

CONTROL

PCOR.3

PCDDR.3

IPB BIT

PC3 ei2 INTERRUPT SOURCE

PORT C [3:1] INTERRUPTS

PC3

PC2

PC1

ST7MC1xx/ST7MC2xx

47/309

INTERRUPTS (Cont’d)

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0] ei2 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the following external interrupts:

- ei2 (port C3..1)

- ei2 (port C0, B7..6)

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port C

This bit is used to invert the sensitivity of the port

C[3:1] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bit 4:3= IS2[1:0] ei1sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

- ei1 (port A3, A5...A7)

Bit 2:1= IS3[1:0] ei0sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

IS11 IS10 IPB IS21 IS20 IS31 IS30 IPA

IS11 IS10

External Interrupt Sensitivity

IPB bit =0 IPB bit =1

00 Falling edge &

low level

Rising edge

& high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

ST7MC1xx/ST7MC2xx

48/309

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d)

- ei0 (port D6..4)

- ei0 (port D3..1)

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 0 = IPA Interrupt polarity for port D

This bit is used to invert the sensitivity of the port D

[6:4] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

IS31 IS30

External Interrupt Sensitivity

IPA bit =0 IPA bit =1

00 Falling edge &

low level

Rising edge

& high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

IS31 IS30 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

ST7MC1xx/ST7MC2xx

49/309

INTERRUPTS (Cont’d)

Table 9. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Label 76543210

0024h ISPR0

Reset Value

ei1 ei0 MCC + SI MCES

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

111

0025h ISPR1

Reset Value

MTC C/D MTC R/Z MTC U/CL ei2

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

0026h ISPR2

Reset Value

SCI TIMER B TIMER A SPI

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

0027h ISPR3

Reset Value

PWMART AVD

I1_15

I0_15

I1_14

I0_14

I1_13

I0_13

I1_12

I0_12

0028h EICR

Reset Value

IS11

IS10

IPB

IS21

IS20

IPA

000

ST7MC1xx/ST7MC2xx

50/309

8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the applica-

tion in terms of power consumption, four main

power saving modes are implemented in the ST7

(see Figure 25): Slow, Wait (Slow-wait), Active-

halt and Halt.

After a RESET the normal operating mode is se-

lected by default (Run mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided or multiplied by 2

(fOSC2).

From Run mode, the different power saving

modes may be selected by setting the relevant

instruction whose action depends on the oscillator

status.

Figure 25. Power Saving Mode Transitions

8.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (fCPU) to

the available supply voltage.

Slow mode is controlled by three bits in the MCC-

SR register: the SMS bit which enables or disables

Slow mode and two CPx bits which select the in-

ternal slow frequency (fCPU).

In this mode, the master clock frequency (fOSC2)

can be divided by 2, 4, 8 or 16. The CPU and pe-

ripherals are clocked at this lower frequency

(fCPU).

Note: Slow-wait mode is activated when entering

the Wait mode while the device is already in Slow

mode.

Figure 26. Slow Mode Clock Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

00 01

SMS

CP1:0

fCPU

NEW SLOW

NORMAL RUN MODE

MCCSR

FREQUENCY

REQUEST

fOSC2

fOSC2/2 fOSC2/4 fOSC2

ST7MC1xx/ST7MC2xx

51/309

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

Wait mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

‘WFI’ instruction.

All peripherals remain active. During Wait mode,

the I[1:0] bits of the CC register are forced to ‘10’,

to enable all interrupts. All other registers and

memory remain unchanged. The MCU remains in

Wait mode until an interrupt or RESET occurs,

whereupon the Program Counter branches to the

starting address of the interrupt or Reset service

routine.

The MCU will remain in Wait mode until a Reset or

an Interrupt occurs, causing it to wake up.

Refer to Figure 27.

Figure 27. Wait Mode Flow-chart

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 1)

256 OR 4096 CPU CLOCK

CYCLE DELAY

+ CYCLE DELAY + E]

ST7MC1xx/ST7MC2xx

52/309

POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

Active-halt and Halt modes are the two lowest

power consumption modes of the MCU. They are

both entered by executing the ‘HALT’ instruction.

The decision to enter either in Active-halt or Halt

mode is given by the MCC/RTC interrupt enable

flag (OIE bit in MCCSR register).

8.4.1 ACTIVE-HALT MODE

Active-halt mode is the lowest power consumption

mode of the MCU with a real-time clock available.

It is entered by executing the ‘HALT’ instruction

when the OIE bit of the Main Clock Controller Sta-

tus register (MCCSR) is set (see section 6.4 on

page 37 for more details on the MCCSR register).

The MCU can exit Active-halt mode on reception

of either an MCC/RTC interrupt, a specific inter-

rupt (see Table 8, “Interrupt Mapping,” on

page 44) or a RESET. When exiting Active-halt

mode by means of an interrupt, no 256 or 4096

CPU cycle delay occurs. The CPU resumes oper-

ation by servicing the interrupt or by fetching the

reset vector which woke it up (see Figure 29).

When entering Active-halt mode, the I[1:0] bits in

the CC register are forced to ‘10b’ to enable inter-

rupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

In Active-halt mode, only the main oscillator and its

associated counter (MCC/RTC) are running to

keep a wake-up time base. All other peripherals

are not clocked except those which get their clock

supply from another clock generator (such as ex-

ternal or auxiliary oscillator).

The safeguard against staying locked in Active-

halt mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering Active-halt mode while the Watchdog is

active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

Figure 28. Active-halt Timing Overview

Figure 29. Active-halt Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits Active-

halt mode by means of a RESET.

2. Peripheral clocked with an external clock source

can still be active.

3. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from Active-halt mode

(such as external interrupt). Refer to Table 8, “In-

terrupt Mapping,” on page 44 for more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 Halt mode

1 Active-halt mode

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY 1)

RESET

INTERRUPT

HALT

INSTRUCTION FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

HALT INSTRUCTION (MCCSR.OIE=0 ENABLE V —> V V V E]

ST7MC1xx/ST7MC2xx

53/309

POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

The Halt mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see section 6.4 on page 37 for more de-

tails on the MCCSR register).

The MCU can exit Halt mode on reception of either

a specific interrupt (see Table 8, “Interrupt Map-

ping,” on page 44) or a RESET. When exiting Halt

mode by means of a RESET or an interrupt, the

oscillator is immediately turned on and the 256 or

4096 CPU cycle delay is used to stabilize the os-

cillator. After the start up delay, the CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 31).

When entering Halt mode, the I[1:0] bits in the CC

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

In Halt mode, the main oscillator is turned off caus-

ing all internal processing to be stopped, including

the operation of the on-chip peripherals. All periph-

erals are not clocked except the ones which get

their clock supply from another clock generator

(such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with Halt

mode is configured by the “WDGHALT” option bit

of the option byte. The HALT instruction when ex-

ecuted while the Watchdog system is enabled, can

generate a Watchdog RESET (see section 14.1 on

page 290 for more details).

Figure 30. Halt Timing Overview

Figure 31. Halt Mode Flow-chart

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from Halt mode (such as external interrupt). Refer

to Table 8, “Interrupt Mapping,” on page 44 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1) 0

WATCHDOG

RESET

(MCCSR.OIE=0)

CYCLE

ST7MC1xx/ST7MC2xx

54/309

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

programmed independently as digital input (with or

without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has two main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: Bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to the I/O Port Implementa-

tion section). The generic I/O block diagram is

shown in Figure 32

9.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Different input modes can be selected by software

through the OR register.

Notes:

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. When switching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

3. Do not use read/modify/write instructions (BSET

or BRES) to modify the DR register as this might

corrupt the DR content for I/Os configured as input.

External interrupt function

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the

EICR register.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several input pins are se-

lected simultaneously as interrupt sources, these

are first detected according to the sensitivity bits in

the EICR register and then logically ORed.

The external interrupts are hardware interrupts,

which means that the request latch (not accessible

directly by the application) is automatically cleared

when the corresponding interrupt vector is

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the EICR register

must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR reg-

ister returns the previously stored value.

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

DR register value and output pin status:

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over the

standard I/O programming.

When the signal is coming from an on-chip periph-

eral, the I/O pin is automatically configured in out-

put mode (push-pull or open drain according to the

peripheral).

When the signal is going to an on-chip peripheral,

the I/O pin must be configured in input mode. In

this case, the pin state is also digitally readable by

addressing the DR register.

Note: Input pull-up configuration can cause unex-

pected value at the input of the alternate peripheral

input. When an on-chip peripheral use a pin as in-

put and output, this pin has to be configured in in-

put floating mode.

DR Push-pull Open-drain

SS Vss

DD Floating

/2g f \ E/ j)? M 9 ““““““““ a

ST7MC1xx/ST7MC2xx

55/309

I/O PORTS (Cont’d)

Figure 32. I/O Port General Block Diagram

Table 10. I/O Port Mode Options

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to VDD is not implemented in the

true open drain pads. A local protection between

the pad and VSS is implemented to protect the de-

vice against positive stress.

Configuration Mode Pull-Up P-Buffer Diodes

to VDD to VSS

Input Floating with/without Interrupt Off Off

On On

Pull-up with/without Interrupt On

Output

Push-pull Off On

Open Drain (logic level) Off

True Open Drain NI NI NI (see note)

DDR

DATA BUS

PAD

VDD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT 1

OR SEL

DDR SEL

DR SEL

PULL-UP

CONDITION

P-BUFFER

(see table below)

N-BUFFER

PULL-UP

(see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

VDD

DIODES

(see table below)

EXTERNAL

SOURCE (eix)

INTERRUPT

CMOS

SCHMITT

TRIGGER

ACCESS

ST7MC1xx/ST7MC2xx

56/309

I/O PORTS (Cont’d)

Table 11. I/O Port Configurations

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

Hardware Configuration

INPUT 1)

OPEN-DRAIN OUTPUT 2)

PUSH-PULL OUTPUT 2)

CONDITION

PAD

VDD

RPU

EXTERNAL INTERRUPT

DATA BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

SOURCE (eix)

CONDITION

ALTERNATE INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

ANALOG INPUT

PAD

RPU

DATA BUS

DR REGISTER ACCESS

R/W

VDD

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

PAD

RPU

DATA BUS

DR REGISTER ACCESS

R/W

VDD

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

E] OHOHOHO

ST7MC1xx/ST7MC2xx

57/309

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage present on the select-

ed pin to the common analog rail which is connect-

ed to the ADC input.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put or true open drain.

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 33 on page 57. Other

transitions are potentially risky and should be

avoided, since they are likely to present unwanted

side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O Port State Transitions

9.4 LOW POWER MODES

9.5 INTERRUPTS

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in

the CC register is not active (RIM instruction).

Mode Description

Wait No effect on I/O ports. External interrupts

cause the device to exit from Wait mode.

Halt No effect on I/O ports. External interrupts

cause the device to exit from Halt mode.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on

selected external

event

-DDRx

ORx Yes

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

XX = DDR, OR

ST7MC1xx/ST7MC2xx

58/309

I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation

The I/O port register configurations are summa-

rised as follows.

Standard Ports

PA4, PA2:0, PB5:0, PC7:4,

PD7:6, PE5:0, PF5:0, PG7:0, PH7:0

Interrupt Ports

PA6, PA3, PB6, PC3, PC1, PD5, PD4, PD2 (with

pull-up)

PA7, PA5, PB7, PC2, PC0, PD6, PD3, PD1 (with-

out pull-up)

Table 12. Port Configuration

MODE DDR OR

floating input 0 0

pull-up input 0 1

open drain output 1 0

push-pull output 1 1

MODE DDR OR

floating input 0 0

pull-up interrupt input 0 1

open drain output 1 0

push-pull output 1 1

MODE DDR OR

floating input 0 0

floating interrupt input 0 1

open drain output 1 0

push-pull output 1 1

Port Pin name Input Output

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA7, PA5 floating floating interrupt open drain push-pull

PA6, PA3 floating pull-up interrupt open drain push-pull

PA2:0 floating pull-up open drain push-pull

Port B

PB7 floating floating interrupt open drain push-pull

PB6 floating pull-up interrupt open drain push-pull

PB5:0 floating pull-up open drain push-pull

Port C

PC7:4 floating pull-up open drain push-pull

PC3, PC1 floating pull-up interrupt open drain push-pull

PC2, PC0 floating floating interrupt open drain push-pull

Port D

PD7, PD0 floating pull-up open drain push-pull

PD6, PD3, PD1 floating floating interrupt open drain push-pull

PD5, PD4, PD2 floating pull-up interrupt open drain push-pull

Port E PE5:0 floating pull-up open drain push-pull

Port F PF5:0 floating pull-up open drain push-pull

Port G PG7:0 floating pull-up open drain push-pull

Port H PH7:0 floating pull-up open drain push-pull

ST7MC1xx/ST7MC2xx

59/309

I/O PORTS (Cont’d)

Table 13. I/O Port Register Map and Reset Values

Address

(Hex.)

Label 76543210

Reset Value

of all I/O port registers 00000000

0000h PADR

MSB LSB0001h PADDR

0002h PAOR

0003h PBDR

MSB LSB0004h PBDDR

0005h PBOR

0006h PCDR

MSB LSB0007h PCDDR

0008h PCOR

0009h PDDR

MSB LSB000Ah PDDDR

000Bh PDOR

000Ch PEDR

MSB LSB000Dh PEDDR

000Eh PEOR

000Fh PFDR

MSB LSB0010h PFDDR

0011h PFOR

0012h PGDR

MSB LSB0013h PGDDR

0014h PGOR

0015h PHDR

MSB LSB0016h PHDDR

0017h PHOR

ST7MC1xx/ST7MC2xx

60/309

10 ON-CHIP PERIPHERALS

10.1 WINDOW WATCHDOG (WWDG)

10.1.1 Introduction

The Window Watchdog is used to detect the oc-

currence of a software fault, usually generated by

external interference or by unforeseen logical con-

ditions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the contents of the downcounter before the T6

bit becomes cleared. An MCU reset is also gener-

ated if the 7-bit downcounter value (in the control

reached the window register value. This implies

that the counter must be refreshed in a limited win-

dow.

10.1.2 Main Features

■Programmable free-running downcounter

■Conditional reset

– Reset (if watchdog activated) when the down-

counter value becomes less than 40h

– Reset (if watchdog activated) if the downcoun-

ter is reloaded outside the window (see Figure

37)

■Hardware/Software Watchdog activation

(selectable by option byte)

■Optional reset on HALT instruction

(configurable by option byte)

10.1.3 Functional Description

The counter value stored in the WDGCR register

(bits T[6:0]), is decremented every 16384 fOSC2

cycles (approx.), and the length of the timeout pe-

riod can be programmed by the user in 64 incre-

ments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit downcounter (T[6:0] bits) rolls

over from 40h to 3Fh (T6 becomes cleared), it ini-

tiates a reset cycle pulling low the reset pin for typ-

ically 30μs. If the software reloads the counter

while the counter is greater than the value stored

in the window register, then a reset is generated.

Figure 34. Watchdog Block Diagram

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

T6 T0

WATCHDOG CONTROL REGISTER (WDGCR)

-W6 W0

WATCHDOG WINDOW REGISTER (WDGWR)

comparator

T6:0 > W6:0 CMP

= 1 when

Write WDGCR

WDG PRESCALER

DIV 4

fOSC2

12-BIT MCC

RTC COUNTER

MSB LSB

DIV 64

MCC/RTC

TB[1:0] bits

(MCCSR

ST7MC1xx/ST7MC2xx

61/309

WINDOW WATCHDOG (Cont’d)

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This operation

must occur only when the counter value is lower

than the window register value. The value to be

stored in the WDGCR register must be between

FFh and C0h (see Figure 35):

– Enabling the watchdog:

When Software Watchdog is selected (by option

byte), the watchdog is disabled after a reset. It is

enabled by setting the WDGA bit in the WDGCR

by a reset.

When Hardware Watchdog is selected (by option

byte), the watchdog is always active and the

WDGA bit is not used.

– Controlling the downcounter:

This downcounter is free-running: It counts down

even if the watchdog is disabled. When the

watchdog is enabled, the T6 bit must be set to

prevent generating an immediate reset.

The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 35. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see Figure 36).

The window register (WDGWR) contains the

high limit of the window: To prevent a reset, the

downcounter must be reloaded when its value is

lower than the window register value and greater

than 3Fh. Figure 37 describes the window watch-

dog process.

Note: The T6 bit can be used to generate a soft-

ware reset (the WDGA bit is set and the T6 bit is

cleared).

– Watchdog Reset on Halt option

If the watchdog is activated and the watchdog re-

set on halt option is selected, then the HALT in-

struction will generate a Reset.

10.1.4 Using Halt Mode with the WDG

If Halt mode with Watchdog is enabled by option

byte (no watchdog reset on HALT instruction), it is

recommended before executing the HALT instruc-

tion to refresh the WDG counter, to avoid an unex-

pected WDG reset immediately after waking up

the microcontroller.

ST7MC1xx/ST7MC2xx

62/309

WINDOW WATCHDOG (Cont’d)

10.1.5 How to Program the Watchdog Timeout

Figure 35 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Coun-

ter (CNT) and the resulting timeout duration in mil-

liseconds. This can be used for a quick calculation

without taking the timing variations into account. If

more precision is needed, use the formulae in Fig-

ure 36.

Caution: When writing to the WDGCR register, al-

ways write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 35. Approximate Timeout Duration

CNT Value (hex.)

Watchdog timeout (ms) @ 8 MHz fOSC2

128

1.5 65

503418 82 98 114

E‘ E]

ST7MC1xx/ST7MC2xx

63/309

WINDOW WATCHDOG (Cont’d)

Figure 36. Exact Timeout Duration (tmin and tmax)

WHERE:

tmin0 = (LSB + 128) x 64 x tOSC2

tmax0 = 16384 x tOSC2

tOSC2 = 125ns if fOSC2 =8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

To calculate the minimum Watchdog Timeout (tmin):

IF THEN

ELSE

To calculate the maximum Watchdog Timeout (tmax):

IF THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.)

TB0 Bit

(MCCSR Reg.)

Selected MCCSR

Timebase MSB LSB

0 0 2ms 4 59

0 1 4ms 8 53

1 0 10ms 20 35

1 1 25ms 49 54

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

tmin

Max. Watchdog

Timeout (ms)

tmax

00 1.496 2.048

3F 128 128.552

CNT MSB

-------------

tmin tmin0 16384 CNT tosc2

××+

tmin tmin0 16384 CNT 4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

×192 LSB+()64 4CNT

MSB

-----------------

××

+tosc2

×+=

CNT MSB

-------------

≤

tmax tmax0 16384 CNT tosc2

××+=

tmax tmax0 16384 CNT 4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

×192 LSB+()64 4CNT

MSB

-----------------

××

+tosc2

×+=

ST7MC1xx/ST7MC2xx

64/309

WINDOW WATCHDOG (Cont’d)

Figure 37. Window Watchdog Timing Diagram

10.1.6 Low Power Modes

10.1.7 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

10.1.8 Using Halt Mode with the WDG

(WDGHALT option)

The following recommendation applies if Halt

mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

T6 bit

Reset

WDGWR

T[5:0] CNT downcounter

time

Refresh WindowRefresh not allowed

(step = 16384/f

OSC2

)

3Fh

Mode Description

Slow No effect on Watchdog: The downcounter continues to decrement at normal speed.

Wait No effect on Watchdog: The downcounter continues to decrement.

Halt

OIE bit in

MCCSR

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

If an interrupt is received (refer to interrupt table mapping to see interrupts

which can occur in halt mode), the Watchdog restarts counting after 256 or

4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 10.1.8 below.

0 1 A reset is generated instead of entering halt mode.

Active-

halt 1x

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

ST7MC1xx/ST7MC2xx

65/309

WINDOW WATCHDOG (Cont’d)

10.1.9 Interrupts

None.

10.1.10 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

counter. It is decremented every 16384 fOSC2 cy-

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

WINDOW REGISTER (WDGWR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = Reserved

Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be com-

pared to the downcounter.

WDGA T6 T5 T4 T3 T2 T1 T0

- W6W5W4W3W2W1W0

ST7MC1xx/ST7MC2xx

66/309

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Label 76543210

002Ah WDGCR

Reset Value

WDGA

002Bh WDGWR

Reset Value

ST7MC1xx/ST7MC2xx

67/309

10.2 PWM AUTO-RELOAD TIMER (ART)

10.2.1 Introduction

The Pulse Width Modulated Auto-Reload Timer

on-chip peripheral consists of an 8-bit auto reload

counter with compare/capture capabilities and of a

7-bit prescaler clock source.

These resources allow five possible operating

modes:

– Generation of up to 4 independent PWM signals

– Output compare and Time base interrupt

– Up to two input capture functions

– External event detector

– Up to two external interrupt sources

The three first modes can be used together with a

single counter frequency.

The timer can be used to wake up the MCU from

Wait and Halt modes.

Figure 38. PWM Auto-Reload Timer Block Diagram

OVF INTERRUPT

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR

fINPUT

PWMx

PORT

FUNCTION

ALTERNATE

OCRx

COMPARE

PROGRAMMABLE

PRESCALER

8-BIT COUNTER

(CAR REGISTER)

ARR

ICRx

LOAD

OPx

POLARITY

CONTROL

OEx

PWMCR

MUX

fCPU

DCRx

LOAD

fCOUNTER

ARTCLK fEXT

ARTICx

ICFxICSx ICCSR

LOAD

ICx INTERRUPT

ICIEx

INPUT CAPTURE

CONTROL

ST7MC1xx/ST7MC2xx

68/309

ON-CHIP PERIPHERALS (Cont’d)

10.2.2 Functional Description

Counter

The free running 8-bit counter is fed by the output

of the prescaler, and is incremented on every ris-

ing edge of the clock signal.

It is possible to read or write the contents of the

counter on the fly by reading or writing the Counter

Access register (ARTCAR).

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the

ARTARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

fCOUNTER = fINPUT / 2CC[2:0]

The timer counter’s input clock (fINPUT) feeds the

7-bit programmable prescaler, which selects one

of the 8 available taps of the prescaler, as defined

by CC[2:0] bits in the Control/Status Register

(ARTCSR). Thus the division factor of the prescal-

er can be set to 2n (where n = 0, 1,..7).

This fINPUT frequency source is selected through

the EXCL bit of the ARTCSR register and can be

either the fCPU or an external input frequency fEXT.

The clock input to the counter is enabled by the

TCE (Timer Counter Enable) bit in the ARTCSR

stopped and the prescaler and counter contents

are frozen. When TCE is set, the counter runs at

the rate of the selected clock source.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are

cleared and fINPUT = fCPU.

The counter can be initialized by:

– Writing to the ARTARR register and then setting

the FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the ARTCSR reg-

ister.

– Writing to the ARTCAR counter access register,

In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.

Direct access to the prescaler is not possible.

Output compare control

The timer compare function is based on four differ-

ent comparisons with the counter (one for each

PWMx output). Each comparison is made be-

tween the counter value and an output compare

be accessed directly, it is loaded from the duty cy-

cle register (PWMDCRx) at each overflow of the

counter.

This double buffering method avoids glitch gener-

ation when changing the duty cycle on the fly.

Figure 39. Output compare control

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh

ARTARR=FDh

fCOUNTER

OCRx

PWMDCRx FDh FEh

FDh FEh

FFh

PWMx

mwkznou 5150 iii a

ST7MC1xx/ST7MC2xx

69/309

ON-CHIP PERIPHERALS (Cont’d)

Independent PWM signal generation

This mode allows up to four Pulse Width Modulat-

ed signals to be generated on the PWMx output

pins with minimum core processing overhead.

This function is stopped during Halt mode.

Each PWMx output signal can be selected inde-

pendently using the corresponding OEx bit in the

PWM Control register (PWMCR). When this bit is

set, the corresponding I/O pin is configured as out-

put push-pull alternate function.

The PWM signals all have the same frequency

which is controlled by the counter period and the

ARTARR register value.

fPWM = fCOUNTER / (256 - ARTARR)

When a counter overflow occurs, the PWMx pin

level is changed depending on the corresponding

OPx (output polarity) bit in the PWMCR register.

When the counter reaches the value contained in

one of the output compare register (OCRx) the

corresponding PWMx pin level is restored.

It should be noted that the reload values will also

affect the value and the resolution of the duty cycle

of the PWM output signal. To obtain a signal on a

PWMx pin, the contents of the OCRx register must

be greater than the contents of the ARTARR reg-

ister.

The maximum available resolution for the PWMx

duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the

ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by

changing the polarity.

Figure 40. PWM Auto-reload Timer Function

Figure 41. PWM Signal from 0% to 100% Duty Cycle

DUTY CYCLE

AUTO-RELOAD

PWMx OUTPUT

255

000

WITH OEx=1

AND OPx=0

(ARTARR)

(PWMDCRx)

WITH OEx=1

AND OPx=1

COUNTER

PWMx OUTPUT

WITH OEx=1

AND OPx=0

FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARTARR=FDh

fCOUNTER

IMMMHMMA M M

ST7MC1xx/ST7MC2xx

70/309

ON-CHIP PERIPHERALS (Cont’d)

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register

is set and an overflow interrupt request is generat-

ed if the overflow interrupt enable bit, OIE, in the

ARTCSR register, is set. The OVF flag must be re-

set by the user software. This interrupt can be

used as a time base in the application.

External clock and event detector mode

Using the fEXT external prescaler input clock, the

auto-reload timer can be used as an external clock

event detector. In this mode, the ARTARR register

is used to select the nEVENT number of events to

be counted before setting the OVF flag.

nEVENT = 256 - ARTARR

Caution: The external clock function is not availa-

ble in Halt mode. If Halt mode is used in the appli-

cation, prior to executing the HALT instruction, the

counter must be disabled by clearing the TCE bit

in the ARTCSR register to avoid spurious counter

increments.

Figure 42. External Event Detector Example (3 counts)

COUNTER

FDh FEh FFh FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR=FDh

fEXT=fCOUNTER

FEh FFh FDh

IF OIE=1

INTERRUPT

IF OIE=1

ARTCSR READ

>------33 xxh 04h E]

ST7MC1xx/ST7MC2xx

71/309

ON-CHIP PERIPHERALS (Cont’d)

Input capture function

This mode allows the measurement of external

signal pulse widths through ARTICRx registers.

Each input capture can generate an interrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the corresponding

CFx bits of the Input Capture Control/Status regis-

ter (ARTICCSR).

These input capture interrupts are enabled

through the CIEx bits of the ARTICCSR register.

The active transition (falling or rising edge) is soft-

ware programmable through the CSx bits of the

ARTICCSR register.

The read only input capture registers (ARTICRx)

are used to latch the auto-reload counter value

when a transition is detected on the ARTICx pin

(CFx bit set in ARTICCSR register). After fetching

the interrupt vector, the CFx flags can be read to

identify the interrupt source.

Note: After a capture detection, data transfer in

the ARTICRx register is inhibited until it is read

(clearing the CFx bit).

The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

set). This means, the ARTICRx register has to be

read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/fCOUNTER).

Note: During Halt mode, if both input capture and

external clock are enabled, the ARTICRx register

value is not guaranteed if the input capture pin and

the external clock change simultaneously.

External interrupt capability

This mode allows the Input capture capabilities to

be used as external interrupt sources. The inter-

rupts are generated on the edge of the ARTICx

signal.

The edge sensitivity of the external interrupts is

programmable (CSx bit of ARTICCSR register)

and they are independently enabled through CIEx

bits of the ARTICCSR register. After fetching the

interrupt vector, the CFx flags can be read to iden-

tify the interrupt source.

During Halt mode, the external interrupts can be

used to wake up the micro (if the CIEx bit is set).

Figure 43. Input Capture Timing Diagram

04h

COUNTER

01h

fCOUNTER

xxh

02h 03h 05h 06h 07h

04h

ARTICx PIN

CFx FLAG

ICRx REGISTER

INTERRUPT

ST7MC1xx/ST7MC2xx

72/309

ON-CHIP PERIPHERALS (Cont’d)

10.2.3 Register Description

CONTROL / STATUS REGISTER (ARTCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EXCL External Clock

This bit is set and cleared by software. It selects the

input clock for the 7-bit prescaler.

0: CPU clock.

1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control

These bits are set and cleared by software. They

determine the prescaler division ratio from fINPUT.

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the

timer in the lowest power consumption mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter running.

Bit 2 = FCRL Force Counter Re-Load

This bit is write-only and any attempt to read it will

yield a logical zero. When set, it causes the contents

of ARTARR register to be loaded into the counter,

and the content of the prescaler register to be

cleared in order to initialize the timer before starting

to count.

Bit 1 = OIE Overflow Interrupt Enable

This bit is set and cleared by software. It allows to

enable/disable the interrupt which is generated

when the OVF bit is set.

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

Bit 0 = OVF Overflow Flag

This bit is set by hardware and cleared by software

reading the ARTCSR register. It indicates the tran-

sition of the counter from FFh to the ARTARR val-

ue.

0: New transition not yet reached

1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = CA[7:0] Counter Access Data

These bits can be set and cleared either by hard-

ware or by software. The ARTCAR register is used

to read or write the auto-reload counter “on the fly”

(while it is counting).

AUTO-RELOAD REGISTER (ARTARR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = AR[7:0] Counter Auto-Reload Data

These bits are set and cleared by software. They

are used to hold the auto-reload value which is au-

tomatically loaded in the counter when an overflow

occurs. At the same time, the PWM output levels

are changed according to the corresponding OPx

bit in the PWMCR register.

This register has two PWM management func-

tions:

– Adjusting the PWM frequency

– Setting the PWM duty cycle resolution

PWM Frequency vs Resolution:

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

fCOUNTER With fINPUT=8 MHz CC2 CC1 CC0

fINPUT

fINPUT / 2

fINPUT / 4

fINPUT / 8

fINPUT / 16

fINPUT / 32

fINPUT / 64

fINPUT / 128

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

125 kHz

62.5 kHz

CA7CA6CA5CA4CA3CA2CA1CA0

AR7AR6AR5AR4AR3AR2AR1AR0

ARTARR

value Resolution

fPWM

Min Max

0 8-bit ~0.244 kHz 31.25 kHz

[ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz

[ 128..191 ] > 6-bit ~0.488 kHz 125 kHz

[ 192..223 ] > 5-bit ~0.977 kHz 250 kHz

[ 224..239 ] > 4-bit ~1.953 kHz 500 kHz

£7

ST7MC1xx/ST7MC2xx

73/309

ON-CHIP PERIPHERALS (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = OE[3:0] PWM Output Enable

These bits are set and cleared by software. They

enable or disable the PWM output channels inde-

pendently acting on the corresponding I/O pin.

0: PWM output disabled.

1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Polarity

These bits are set and cleared by software. They

independently select the polarity of the four PWM

output signals.

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

A PWMDCRx register is associated with the OCRx

second edge location of the PWM signal (the first

edge location is common to all channels and given

by the ARTARR register). These PWMDCR regis-

ters allow the duty cycle to be set independently

for each PWM channel.

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

PWMx output level

OPx

Counter <= OCRx Counter > OCRx

100

011

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

ST7MC1xx/ST7MC2xx

74/309

ON-CHIP PERIPHERALS (Cont’d)

INPUT CAPTURE

CONTROL / STATUS REGISTER (ARTICCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved, always read as 0.

Bit 5:4 = CS[2:1] Capture Sensitivity

These bits are set and cleared by software. They

determine the trigger event polarity on the corre-

sponding input capture channel.

0: Falling edge triggers capture on channel x.

1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They

enable or disable the Input capture channel inter-

rupts independently.

0: Input capture channel x interrupt disabled.

1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware and cleared by

software reading the corresponding ARTICRx reg-

ister. Each CFx bit indicates that an input capture x

has occurred.

0: No input capture on channel x.

1: An input capture has occurred on channel x.

INPUT CAPTURE REGISTERS (ARTICRx)

Read only

Reset Value: 0000 0000 (00h)

Bit 7:0 = IC[7:0] Input Capture Data

These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit

auto-reload counter value transferred by the input

capture channel x event.

0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

ST7MC1xx/ST7MC2xx

75/309

PWM AUTO-RELOAD TIMER (Cont’d)

Table 15. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

Label 76543210

0074h PWMDCR3

Reset Value

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

0075h PWMDCR2

Reset Value

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

0076h PWMDCR1

Reset Value

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

0077h PWMDCR0

Reset Value

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

0078h PWMCR

Reset Value

OE3

OE2

OE1

OE0

OP3

OP2

OP1

OP0

0079h ARTCSR

Reset Value

EXCL

CC2

CC1

CC0

TCE

FCRL

OIE

OVF

007Ah ARTCAR

Reset Value

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

007Bh ARTARR

Reset Value

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

007Ch ARTICCSR

Reset Value 00

CS2

CS1

CIE2

CIE1

CF2

CF1

007Dh ARTICR1

Reset Value

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

007Eh ARTICR2

Reset Value

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

ST7MC1xx/ST7MC2xx

76/309

10.3 16-BIT TIMER

10.3.1 Introduction

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Some devices of the ST7 family have two on-chip

16-bit timers. They are completely independent,

and do not share any resources. They are syn-

chronized after a Device reset as long as the timer

clock frequencies are not modified.

This description covers one or two 16-bit timers. In

the devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main Features

■Programmable prescaler: fCPU divided by 2, 4 or 8.

■Overflow status flag and maskable interrupt

■External clock input (must be at least 4 times

slower than the CPU clock speed) with the choice

of active edge

■Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■Pulse width modulation mode (PWM)

■One pulse mode

■Reduced Power Mode

■5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 44.

*Note: Some timer pins may not available (not

bonded) in some devices. Refer to the device pin

out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

10.3.3 Functional Description

10.3.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the counter register re-

peats every 131 072, 262 144 or 524 288 CPU

clock cycles depending on the CC[1:0] bits.

The timer frequency can be fCPU/2, fCPU/4, fCPU/8

or an external frequency.

LATC H1

ST7MC1xx/ST7MC2xx

77/309

16-BIT TIMER (Cont’d)

Figure 44. Timer Block Diagram

16-BIT TIMER PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2

1/4

1/8

8-bit

buffer

INTERNAL BUS

LATCH1 OCMP1

ICAP1

EXTCLK

fCPU

TIMER INTERRUPT

ICF2ICF1 TIMD 00

OCF2OCF1 TOF

PWMOC1E EXEDG

IEDG2CC0CC1

OC2E OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

ICAP2

LATCH2 OCMP2

8 low

8 high

16 16

(Control Register 1) CR1 (Control Register 2) CR2

(Control/Status Register)

8 8 8

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT

COMPARE

INPUT

CAPTURE

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See Device Interrupt Vector Table)

(See note)

CSR

7771 LiviJ

ST7MC1xx/ST7MC2xx

78/309

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

The timer is not affected by Wait mode.

In Halt mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (Device awakened by an interrupt)

or from the reset count (Device awakened by a

Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

The counter is synchronised with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

is buffered

Read

At t0

Read Returns the buffered

LS Byte value at t0

At t0 +Δt

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

ST7MC1xx/ST7MC2xx

79/309

16-BIT TIMER (Cont’d)

Figure 45. Counter Timing Diagram, internal clock divided by 2

Figure 46. Counter Timing Diagram, internal clock divided by 4

Figure 47. Counter Timing Diagram, internal clock divided by 8

Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-

ning.

CPU CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000

ST7MC1xx/ST7MC2xx

80/309

16-BIT TIMER (Cont’d)

10.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

ICiR register is a read-only register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

counter: (fCPU/CC[1:0]).

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input).

When an input capture occurs:

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 49).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user toggle

the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer

range (FFFFh).

MS Byte LS Byte

ICiR ICiHR ICiLR

ST7MC1xx/ST7MC2xx

81/309

16-BIT TIMER (Cont’d)

Figure 48. Input Capture Block Diagram

Figure 49. Input Capture Timing Diagram

Note: The time between an event on the ICAPi pin

and the appearance of the corresponding flag is

from 2 to 3 CPU clock cycles. This depends on the

moment when the ICAP event happens relative to

the timer clock.

ICIE

CC0

CC1

16-BIT FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

16-BIT

IC1R Register

IC2R Register

EDGE DETECT

CIRCUIT1

FF01 FF02 FF03

FF03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The active edge is the rising edge.

ST7MC1xx/ST7MC2xx

82/309

16-BIT TIMER (Cont’d)

10.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

Timing resolution is one count of the free running

counter: (fCPU/CC[1:0]).

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE bit to generate an interrupt if it is

needed.

When a match is found between OCRi register

and CR register:

– OCFi bit is set.

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

Δt = Output compare period (in seconds)

fCPU = CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock, the formula

is:

Where:

Δt = Output compare period (in seconds)

fEXT = External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

– Write to the OCiHR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

MS Byte LS Byte

OCiROCiHR OCiLR

Δ OCiR = Δt * fCPU

PRESC

Δ OCiR = Δt * fEXT

ST7MC1xx/ST7MC2xx

83/309

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. In both internal and external clock modes, OCFi

and OCMPi are set while the counter value

equals the OCiR register value (see Figure 51

for an example with fCPU/2 and Figure 52 for an

example with fCPU/4). This behavior is the same

in OPM or PWM mode.

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

FOLVLi bits have no effect in both one pulse mode

and PWM mode.

Figure 50. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

TIMER fCPU WWW :é<:>--C —l— J TIMER fCPU —l— —li

ST7MC1xx/ST7MC2xx

84/309

16-BIT TIMER (Cont’d)

Figure 51. Output Compare Timing Diagram, fTIMER =fCPU/2

Figure 52. Output Compare Timing Diagram, fTIMER =fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2 2ED3 2ED42ECF

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)2ED3

2ED0 2ED1 2ED2 2ED3 2ED42ECF

OCMPi PIN (OLVLi=1)

OUTPUT COMPARE FLAG i (OCFi)

E] ‘7

ST7MC1xx/ST7MC2xx

85/309

16-BIT TIMER (Cont’d)

10.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

When a valid event occurs on the ICAP1 pin, the

counter value is loaded in the ICR1 register. The

counter is then initialized to FFFCh, the OLVL2 bit

is output on the OCMP1 pin and the ICF1 bit is set.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Where:

t = Pulse period (in seconds)

fCPU = CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock the formula is:

Where:

t = Pulse period (in seconds)

fEXT = External timer clock frequency (in hertz)

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 53).

Notes:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

event occurs

Counter

= OC1R OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

OCiR Value = t * fCPU

PRESC

- 5

OCiR = t * fEXT -5

2XXXX3£XX XWX ’LA

ST7MC1xx/ST7MC2xx

86/309

16-BIT TIMER (Cont’d)

Figure 53. One Pulse Mode Timing Example

Figure 54. Pulse Width Modulation Mode Timing Example

COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2 OLVL2OLVL1

ICAP1

OCMP1 compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

01F8

01F8 2ED3

IC1R

COUNTER 34E2 34E2 FFFC

OLVL2 OLVL2

OLVL1

compare2 compare1 compare2

Note:

ST7MC1xx/ST7MC2xx

16-BIT TIMER

10.3.3.6 Pulse Width Modulation Mode

Note:

Procedure

Notes:

Pulse Width Modulation cycle

ST7MC1xx/ST7MC2xx

16-BIT TIMER

10.3.4 Low Power Modes

10.3.5 Interrupts

Note:

10.3.6 Summary of Timer modes

3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode

Wait No effect on 16-bit Timer.

Timer interrupts cause the Device to exit from Wait mode.

Halt

16-bit Timer registers are frozen.

In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count

when the Device is woken up by an interrupt with “exit from Halt mode” capability or from the counter reset

value when the Device is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the Device is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and

the counter value present when exiting from Halt mode is captured into the ICiR register.

Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No

Input Capture 2 event ICF2 Yes No

Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No

Output Compare 2 event (not available in PWM mode) OCF2 Yes No

Timer Overflow event TOF TOIE Yes No

Input Capture (1 and/or 2) Yes Yes Yes Yes

Output Compare (1 and/or 2) Yes Yes Yes Yes

One Pulse Mode No Not Recommended1) No Partially 2)

PWM Mode No Not Recommended3) No No

89/309

(Cont’d)

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Bit 3 = Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Bit 2 = Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 1 = Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

90/309

(Cont’d)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

Bit 4 = Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Bit 3, 2 = Clock Control.

The timer clock mode depends on these bits:

: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

fCPU / 4 0 0

fCPU / 2 0 1

fCPU / 8 1 0

External Clock (where

available) 11

91/309

(Cont’d)

Read Only

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

Bit 7 =

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

IC1R (IC1LR) register.

Bit 6 =

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 5 =

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Reading or writing the ACLR register does

not clear TOF.

Bit 4 =

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

Bit 3 =

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 2 =

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

92/309

(Cont’d)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

MSB LSB

93/309

(Cont’d)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

MSB LSB

94/309

(Cont’d)

Timer A: 32

Timer B: 42 Reset Value

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Timer A: 31

Timer B: 41 Reset Value

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Timer A: 33

Timer B: 43 Reset Value

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

Timer A: 34

Timer B: 44 Reset Value

MSB

-------

LSB

Timer A: 35

Timer B: 45 Reset Value

MSB

-------

LSB

Timer A: 36

Timer B: 46 Reset Value

MSB

-------

LSB

Timer A: 37

Timer B: 47 Reset Value

MSB

-------

LSB

Timer A: 3E

Timer B: 4E Reset Value

MSB

-------

LSB

Timer A: 3F

Timer B: 4F Reset Value

MSB

-------

LSB

Timer A: 38

Timer B: 48 Reset Value

MSB

1111111

LSB

Timer A: 39

Timer B: 49 Reset Value

MSB

1111110

LSB

Timer A: 3A

Timer B: 4A Reset Value

MSB

1111111

LSB

Timer A: 3B

Timer B: 4B Reset Value

MSB

1111110

LSB

Timer A: 3C

Timer B: 4C Reset Value

MSB

-------

LSB

Timer A: 3D

Timer B: 4D Reset Value

MSB

-------

LSB

E] nw

95/309

(cont’d)

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

■Full duplex synchronous transfers (on three

lines)

■Simplex synchronous transfers (on two lines)

■Master or slave operation

■6 master mode frequencies (fCPU/4 max.)

■fCPU/2 max. slave mode frequency (see note)

■SS Management by software or hardware

■Programmable clock polarity and phase

■End of transfer interrupt flag

■Write collision, Master Mode Fault and Overrun

flags

In slave mode, continuous transmission is

not possible at maximum frequency due to the

software overhead for clearing status flags and to

initiate the next transmission sequence.

Figure 55 on page 96 shows the serial peripheral

interface (SPI) block diagram. There are three reg-

isters:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

four pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

–SS

: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master Device.

#TTTTFSEETL l—if f? , :T 3+4o—a

96/309

(cont’d)

Read Buffer

8-bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE SPE MSTR CPHA SPR0

SPR1

CPOL

SERIAL CLOCK

GENERATOR

CONTROL

STATE

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL MODF 0

OVR SSISSMSOD

SOD

bit SS 1

97/309

(cont’d)

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 56.

The MOSI pins are connected together and the

MISO pins are connected together. In this way

data is transferred serially between master and

slave (most significant bit first).

The communication is always initiated by the mas-

ter. When the master device transmits data to a

slave device via MOSI pin, the slave device re-

sponds by sending data to the master device via

the MISO pin. This implies full duplex communica-

tion with both data out and data in synchronized

with the same clock signal (which is provided by

the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins

must be connected at each node (in this case only

simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 59 on page 100) but master

and slave must be programmed with the same tim-

ing mode.

8-bit SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-bit SHIFT REGISTER

MISO

MOSI MOSI

MISO

SCK SCK

SS SS

+5V

MSBit LSBit MSBit LSBit

Not used if SS is managed

by software

7 internal m sl_be h mission anons ma merna‘ mnsswo alLo LEA!“ BmeZ

98/309

(cont’d)

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to

manage the Slave Select signal by software. This

is configured by the SSM bit in the SPICSR regis-

ter (see Figure 58).

In software management, the external SS pin is

free for other application uses and the internal SS

signal level is driven by writing to the SSI bit in the

SPICSR register.

–SS

internal must be held high continuously

There are two cases depending on the data/clock

timing relationship (see Figure 57):

If CPHA = 1 (data latched on second clock edge):

–SS

internal must be held low during the entire

transmission. This implies that in single slave

applications the SS pin either can be tied to

VSS, or made free for standard I/O by manag-

ing the SS function by software (SSM = 1 and

SSI = 0 in the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):

–SS

internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to write to the shift reg-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see Section 10.4.5.3).

MOSI/MISO

Master SS

Slave SS

(if CPHA = 0)

Slave SS

(if CPHA = 1)

Byte 1 Byte 2 Byte 3

SS internal

SSM bit

SSI bit

SS external pin

E] née Hon

99/309

(cont’d)

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if

CPOL = 0).

To operate the SPI in master mode, perform the

following steps in order:

1. Write to the SPICR register:

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

59 shows the four possible configurations.

The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

MSTR and SPE bits remain set only if

SS is high).

if the SPICSR register is not writ-

ten first, the SPICR register setting (MSTR bit)

may be not taken into account.

The transmit sequence begins when software

writes a byte in the SPIDR register.

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware.

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register

While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

In slave mode, the serial clock is received on the

SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 59).

The slave must have the same CPOL

and CPHA settings as the master.

– Manage the SS pin as described in Section

10.4.3.2 and Figure 57. If CPHA = 1 SS must

be held low continuously. If CPHA = 0 SS

must be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware.

– An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A write or a read to the SPIDR register

While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an Overrun

condition (see Section 10.4.5.2).

+ + ‘7‘ WWW xafx x xij *W WM YEXIXBXBXBM % §~ “Hf \ f 4 wwxmsxwaxastx max X‘XBXEXWXEXSXXXF

100/309

(cont’d)

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 59).

The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if

CPOL = 0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge.

Figure 59 shows an SPI transfer with the four com-

binations of the CPHA and CPOL bits. The dia-

gram may be interpreted as a master or slave tim-

ing diagram where the SCK pin, the MISO pin and

the MOSI pin are directly connected between the

master and the slave device.

: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

SCK

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1)

SCK

(CPOL = 0)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

we E]

ST7MC1xx/ST7MC2xx

101/309

SERIAL PERIPHERAL INTERFACE (cont’d)

10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master de-

vice’s SS pin is pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software

sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but

in a multimaster configuration the device can be in

slave mode with the MODF bit set.

The MODF bit indicates that there might have

been a multimaster conflict and allows software to

handle this using an interrupt routine and either

perform a reset or return to an application default

state.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs when the master de-

vice has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously

transmitted byte.

When an Overrun occurs:

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

The OVR bit is cleared by reading the SPICSR

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted and

the software write will be unsuccessful.

Write collisions can occur both in master and slave

mode. See also Section 10.4.3.2 Slave Select

Management.

Note: A "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the CPU oper-

ation.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 60).

Figure 60. Clearing the WCOL Bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step Read SPICSR

Read SPIDR

2nd Step SPIF = 0

WCOL = 0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step WCOL = 0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR register in-

stead of reading it does not reset the

WCOL bit.

RESULT

ST7MC1xx/ST7MC2xx

102/309

SERIAL PERIPHERAL INTERFACE (cont’d)

10.4.5.4 Single Master and Multimaster

Configurations

There are two types of SPI systems:

– Single Master System

– Multimaster System

Single Master System

A typical single master system may be configured

using a device as the master and four devices as

slaves (see Figure 61).

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line,

the master allows only one active slave device

during a transmission.

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written to its SPIDR

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

Multimaster System

A multimaster system may also be configured by

the user. Transfer of master control could be im-

plemented using a handshake method through the

I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The multimaster system is principally handled by

the MSTR bit in the SPICR register and the MODF

bit in the SPICSR register.

Figure 61. Single Master / Multiple Slave Configuration

MISO

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS SS SS SS

SCK SCK

SCK

Ports

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

Ex E]

ST7MC1xx/ST7MC2xx

103/309

SERIAL PERIPHERAL INTERFACE (cont’d)

10.4.6 Low Power Modes

10.4.6.1 Using the SPI to wake up the device

from Halt mode

In slave configuration, the SPI is able to wake up

the device from Halt mode through a SPIF inter-

rupt. The data received is subsequently read from

the SPIDR register when the software is running

(interrupt vector fetch). If multiple data transfers

have been performed before software clears the

SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake up the device from

Halt mode only if the Slave Select signal (external

SS pin or the SSI bit in the SPICSR register) is low

when the device enters Halt mode. So, if Slave se-

lection is configured as external (see Section

10.4.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

10.4.7 Interrupts

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

Mode Description

Wait

No effect on SPI.

SPI interrupt events cause the device to exit

from Wait mode.

Halt

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI opera-

tion resumes when the device is woken up by

an interrupt with “exit from Halt mode” capa-

bility. The data received is subsequently read

from the SPIDR register when the software is

running (interrupt vector fetching). If several

data are received before the wake-up event,

then an overrun error is generated. This error

can be detected after the fetch of the inter-

rupt routine that woke up the Device.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of

Transfer Event SPIF

SPIE Yes

Yes

Master Mode

Fault Event MODF No

Overrun Error OVR

clea clea

ST7MC1xx/ST7MC2xx

104/309

10.4.8 Register Description

SPI CONTROL REGISTER (SPICR)

Read/Write

Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Over-

run error occurs (SPIF = 1, MODF = 1 or

OVR = 1 in the SPICSR register)

Bit 6 = SPE

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode,

SS =0 (see Section 10.4.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the ex-

ternal pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2

This bit is set and cleared by software and is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 18 SPI Master

Mode SCK Frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode,

SS =0 (see Section 10.4.5.1 Master Mode Fault

(MODF)).

0: Slave mode

1: Master mode. The function of the SCK pin

changes from an input to an output and the func-

tions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL

This bit is set and cleared by software. This bit de-

termines the idle state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Bit 2 = CPHA

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bits 1:0 = SPR[1:0]

These bits are set and cleared by software. Used

with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master

mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master Mode SCK Frequency

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Serial Clock SPR2 SPR1 SPR0

fCPU/4 1

fCPU/8 0

fCPU/16 1

fCPU/32 1

fCPU/64 0

fCPU/128 1

nagem min as

ST7MC1xx/ST7MC2xx

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SERIAL PERIPHERAL INTERFACE (cont’d)

SPI CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE = 1 in the SPICR register. It is cleared by

a software sequence (an access to the SPICSR

SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

Bit 6 = WCOL

This bit is set by hardware when a write to the

SPIDR register is done during a transmit se-

quence. It is cleared by a software sequence (see

Figure 60).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR S

This bit is set by hardware when the byte currently

being received in the shift register is ready to be

transferred into the SPIDR register while SPIF = 1

(See Section 10.4.5.2). An interrupt is generated if

SPIE = 1 in the SPICR register. The OVR bit is

cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 10.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE = 1 in the SPICR register.

This bit is cleared by a software sequence (An ac-

cess to the SPICSR register while MODF = 1 fol-

lowed by a write to the SPICR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE = 1)

1: SPI output disabled

Bit 1 = SSM

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI SS pin

and uses the SSI bit value instead. See Section

10.4.3.2 Slave Select Management.

0: Hardware management (SS managed by exter-

nal pin)

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin free for gener-

al-purpose I/O)

Bit 0 = SSI

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave

select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

SPI DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

the serial peripheral data I/O register, the buffer is

actually being read.

While the SPIF bit is set, all writes to the SPIDR

read.

Warning: A write to the SPIDR register places

data directly into the shift register for transmission.

A read to the SPIDR register returns the value lo-

cated in the buffer and not the content of the shift

SPIF WCOL OVR MODF - SOD SSM SSI

D7 D6 D5 D4 D3 D2 D1 D0

ST7MC1xx/ST7MC2xx

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

Label 76543210

0021h SPIDR

Reset Value

MSB

xxxxxxx

LSB

0022h SPICR

Reset Value

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

0023h SPICSR

Reset Value

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

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10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)

10.5.1 Introduction

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI of-

fers a very wide range of baud rates using two

baud rate generator systems.

The LIN-dedicated features support the LIN (Local

Interconnect Network) protocol for both master

and slave nodes.

This chapter is divided into SCI Mode and LIN

mode sections. For information on general SCI

communications, refer to the SCI mode section.

For LIN applications, refer to both the SCI mode

and LIN mode sections.

10.5.2 SCI Features

■Full duplex, asynchronous communications

■NRZ standard format (Mark/Space)

■Independently programmable transmit and

receive baud rates up to 500K baud

■Programmable data word length (8 or 9 bits)

■Receive buffer full, Transmit buffer empty and

End of Transmission flags

■2 receiver wake-up modes:

– Address bit (MSB)

– Idle line

■Muting function for multiprocessor configurations

■Separate enable bits for Transmitter and

Receiver

■Overrun, Noise and Frame error detection

■6 interrupt sources

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error

– Parity interrupt

■Parity control:

– Transmits parity bit

– Checks parity of received data byte

■Reduced power consumption mode

10.5.3 LIN Features

– LIN Master

– 13-bit LIN Synch Break generation

– LIN Slave

– Automatic Header Handling

– Automatic baud rate resynchronization based

on recognition and measurement of the LIN

Synch Field (for LIN slave nodes)

– Automatic baud rate adjustment (at CPU fre-

quency precision)

– 11-bit LIN Synch Break detection capability

– LIN Parity check on the LIN Identifier Field

(only in reception)

– LIN Error management

– LIN Header Timeout

– Hot plugging support

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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d)

10.5.4 General Description

The interface is externally connected to another

device by two pins:

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O

port configuration. When the transmitter is ena-

bled and nothing is to be transmitted, the TDO

pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

Through these pins, serial data is transmitted and

received as characters comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the character is com-

plete

This interface uses three types of baud rate gener-

ator:

– A conventional type for commonly-used baud

rates

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard

oscillator frequencies

– A LIN baud rate generator with automatic resyn-

chronization

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

Figure 62. SCI Block Diagram (in Conventional Baud Rate Generator Mode)

WAKE

UNIT

RECEIVER

CONTROL

SCISR

TRANSMIT

CONTROL

TDRE TC RDRF IDLE OR/ NF FE PE

SCI

CONTROL

INTERRUPT

SCICR1

R8 T8 SCID MWAKE PCE PS PIE

Received Data Register (RDR)

Receive Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER) SCIDR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

SCIBRR

SCP1

fCPU

CONTROL

SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

SBKRWURETEILIERIETCIETIE

SCICR2

LHE

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.5 SCI Mode - Functional Description

Conventional Baud Rate Generator Mode

The block diagram of the Serial Control Interface

in conventional baud rate generator mode is

shown in Figure 62.

It uses four registers:

– 2 control registers (SCICR1 and SCICR2)

– A status register (SCISR)

– A baud rate register (SCIBRR)

Extended Prescaler Mode

Two additional prescalers are available in extend-

ed prescaler mode. They are shown in Figure 64.

– An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

10.5.5.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 63).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as a continuous

logic high level for 10 (or 11) full bit times.

A Break character is a character with a sufficient

number of low level bits to break the normal data

format followed by an extra “1” bit to acknowledge

the start bit.

Figure 63. Word Length Programming

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

Start

Bit Stop

Bit

Start

Bit

Idle Line

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start

Bit Stop

Bit

Start

Bit

Start

Bit

Idle Line Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Character Start

Bit

Extra

’1’

Data Character

Break Character Start

Bit

Extra

’1’

Data Character

Next Data Character

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.5.2 Transmitter

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 62).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to send a preamble of 10 (M = 0)

or 11 (M = 1) consecutive ones (Idle Line) as first

transmission.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I[|1:0] bits are cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

When a character transmission is complete (after

the stop bit) the TC bit is set and an interrupt is

generated if the TCIE is set and the I[1:0] bits are

cleared in the CCR register.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break character length de-

pends on the M bit (see Figure 63).

As long as the SBK bit is set, the SCI sends break

characters to the TDO pin. After clearing this bit by

software, the SCI inserts a logic 1 bit at the end of

the last break character to guarantee the recogni-

tion of the start bit of the next character.

Idle Line

Setting the TE bit drives the SCI to send a pream-

ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s

(idle line) before the first character.

In this case, clearing and then setting the TE bit

during a transmission sends a preamble (idle line)

after the current word. Note that the preamble du-

ration (10 or 11 consecutive ‘1’s depending on the

M bit) does not take into account the stop bit of the

previous character.

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set, that is, before writing the next byte in the

SCIDR.

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.5.3 Receiver

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

Character reception

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) be-

tween the internal bus and the received shift regis-

ter (see Figure 62).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and

the I[1:0] bits are cleared in the CCR register.

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

Idle Line

When an idle line is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I[|1:0] bits are

cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

TDR register as long as the RDRF bit is not

cleared.

When an overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I[|1:0] bits are cleared in the CCR register.

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

When noise is detected in a character:

– The NF bit is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The NF bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

Framing Error

A framing error is detected when:

– The stop bit is not recognized on reception at the

expected time, following either a desynchroniza-

tion or excessive noise.

– A break is received.

When the framing error is detected:

– the FE bit is set by hardware

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

Break Character

– When a break character is received, the SCI

handles it as a framing error. To differentiate a

break character from a framing error, it is neces-

sary to read the SCIDR. If the received value is

00h, it is a break character. Otherwise it is a

framing error.

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.5.4 Conventional Baud Rate Generation

The baud rates for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If fCPU is 8 MHz (normal mode) and if

PR = 13 and TR = RR = 1, the transmit and re-

ceive baud rates are 38400 baud.

Note: The baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

10.5.5.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine

tuning on the baud rate, using a 255 value prescal-

er, whereas the conventional Baud Rate Genera-

tor retains industry standard software compatibili-

ty.

The extended baud rate generator block diagram

is described in Figure 64.

The output clock rate sent to the transmitter or to

the receiver will be the output from the 16 divider

divided by a factor ranging from 1 to 255 set in the

SCIERPR or the SCIETPR register.

Note: The extended prescaler is activated by set-

ting the SCIETPR or SCIERPR register to a value

other than zero. The baud rates are calculated as

follows:

with:

ETPR = 1, ..., 255 (see SCIETPR register)

ERPR = 1, ..., 255 (see SCIERPR register)

Tx =

(16*PR)*TR

fCPU Rx =

(16*PR)*RR

fCPU

Tx =

16*ETPR*(PR*TR)

fCPU Rx =

16*ERPR*(PR*RR)

fCPU

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

Figure 64. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER

RECEIVER

SCIETPR

SCIERPR

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

EXTENDED PRESCALER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

SCIBRR

SCP1

fCPU

CONTROL

SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED TRANSMITTER PRESCALER REGISTER

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.5.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non-addressed receivers.

The non-addressed devices may be placed in

sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in

sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

A muted receiver may be woken up in one of the

following ways:

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Idle Line Detection

Receiver wakes up by Idle Line detection when the

Receive line has recognized an Idle Line. Then the

RWU bit is reset by hardware but the IDLE bit is

not set.

This feature is useful in a multiprocessor system

when the first characters of the message deter-

mine the address and when each message ends

by an idle line: As soon as the line becomes idle,

every receivers is waken up and analyse the first

characters of the message which indicates the ad-

dressed receiver. The receivers which are not ad-

dressed set RWU bit to enter in mute mode. Con-

sequently, they will not treat the next characters

constituting the next part of the message. At the

end of the message, an idle line is sent by the

transmitter: this wakes up every receivers which

are ready to analyse the addressing characters of

the new message.

In such a system, the inter-characters space must

be smaller than the idle time.

Address Mark Detection

Receiver wakes up by Address Mark detection

when it received a “1” as the most significant bit of

a word, thus indicating that the message is an ad-

dress. The reception of this particular word wakes

up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this

word normally and to use it as an address word.

This feature is useful in a multiprocessor system

when the most significant bit of each character

(except for the break character) is reserved for Ad-

dress Detection. As soon as the receivers re-

ceived an address character (most significant bit

= ’1’), the receivers are waken up. The receivers

which are not addressed set RWU bit to enter in

mute mode. Consequently, they will not treat the

next characters constituting the next part of the

message.

10.5.5.7 Parity Control

Hardware byte Parity control (generation of parity

bit in transmission and parity checking in recep-

tion) can be enabled by setting the PCE bit in the

SCICR1 register. Depending on the character for-

mat defined by the M bit, the possible SCI charac-

ter formats are as listed in Table 20.

Note: In case of wake-up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

Table 20. Character Formats

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

Even parity: The parity bit is calculated to obtain

an even number of “1s” inside the character made

of the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

will be 0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain

an odd number of “1s” inside the character made

of the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

will be 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS = 0) or an odd number of “1s” if odd parity is

selected (PS = 1). If the parity check fails, the PE

flag is set in the SCISR register and an interrupt is

generated if PCIE is set in the SCICR1 register.

M bit PCE bit Character format

00 | SB | 8 bit data | STB |

1 | SB | 7-bit data | PB | STB |

10 | SB | 9-bit data | STB |

1 | SB | 8-bit data | PB | STB |

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.6 Low Power Modes 10.5.7 Interrupts

The SCI interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

Mode Description

Wait

No effect on SCI.

SCI interrupts cause the device to exit from

Wait mode.

Halt

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/re-

ceiving until Halt mode is exited.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Transmit Data Register

Empty TDRE TIE

Yes No

Transmission Com-

plete TC TCIE

Received Data Ready

to be Read RDRF

RIE

Overrun Error or LIN

Synch Error Detected

OR/

LHE

Idle Line Detected IDLE ILIE

Parity Error PE PIE

LIN Header Detection LHDF LHIE

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

10.5.8 SCI Mode Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Bit 6 = TC

This bit is set by hardware when transmission of a

character containing Data is complete. An inter-

rupt is generated if TCIE = 1 in the SCICR2 regis-

ter. It is cleared by a software sequence (an ac-

cess to the SCISR register followed by a write to

the SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Pre-

amble or a Break.

Bit 5 = RDRF

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR

SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE

This bit is set by hardware when an Idle Line is de-

tected. An interrupt is generated if the ILIE = 1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (that is, a new idle line

occurs).

Bit 3 = OR

The OR bit is set by hardware when the word cur-

rently being received in the shift register is ready to

be transferred into the RDR register whereas

RDRF is still set. An interrupt is generated if

RIE = 1 in the SCICR2 register. It is cleared by a

software sequence (an access to the SCISR regis-

ter followed by a read to the SCIDR register).

0: No Overrun error

1: Overrun error detected

Note: When this bit is set, RDR register contents

will not be lost but the shift register will be overwrit-

ten.

Bit 2 = NF Character Noise flag

This bit is set by hardware when noise is detected

on a received character. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a read to the SCIDR register).

0: No noise

1: Noise is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

Bit 1 = FE Framing error

This bit is set by hardware when a desynchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error

1: Framing error or break character detected

Note: This bit does not generate an interrupt as it

appears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both a frame error and

an overrun error, it will be transferred and only the

OR bit will be set.

Bit 0 = PE Parity error

This bit is set by hardware when a byte parity error

occurs (if the PCE bit is set) in receiver mode. It is

cleared by a software sequence (a read to the sta-

tus register followed by an access to the SCIDR

data register). An interrupt is generated if PIE = 1

in the SCICR1 register.

0: No parity error

1: Parity error detected

TDRE TC RDRF IDLE OR1) NF1) FE1) PE1)

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

1)This bit has a different function in LIN mode, please

refer to the LIN mode register description.

Bit 7 = R8 Receive data bit 8

This bit is used to store the 9th bit of the received

word when M = 1.

Bit 6 = T8 Transmit data bit 8

This bit is used to store the 9th bit of the transmit-

ted word when M = 1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

1: Address Mark

Note: If the LINE bit is set, the WAKE bit is deacti-

vated and replaced by the LHDM bit.

Bit 2 = PCE Parity control enable

This bit is set and cleared by software. It selects

the hardware parity control (generation and detec-

tion for byte parity, detection only for LIN parity).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 = PIE Parity interrupt enable

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). The parity error involved can be a byte

parity error (if bit PCE is set and bit LPE is reset) or

a LIN parity error (if bit PCE is set and bit LPE is

set).

0: Parity error interrupt disabled

1: Parity error interrupt enabled

R8 T8 SCID M WAKE PCE1) PS PIE

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

1)This bit has a different function in LIN mode, please

refer to the LIN mode register description.

Bit 7 = TIE Transmitter interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: In SCI interrupt is generated whenever

TDRE = 1 in the SCISR register

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC = 1

in the SCISR register

Bit 5 = RIE Receiver interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR = 1

or RDRF = 1 in the SCISR register

Bit 4 = ILIE Idle line interrupt enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

IDLE = 1 in the SCISR register.

Bit 3 = TE Transmitter enable

This bit enables the transmitter. It is set and

cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Notes:

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line)

after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

Bit 2 = RE Receiver enable

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled in the SCISR register

1: Receiver is enabled and begins searching for a

start bit

Bit 1 = RWU Receiver wake-up

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

Notes:

– Before selecting Mute mode (by setting the RWU

bit) the SCI must first receive a data byte, other-

wise it cannot function in Mute mode with wake-

up by Idle line detection.

– In Address Mark Detection Wake-Up configura-

tion (WAKE bit = 1) the RWU bit cannot be mod-

ified by software while the RDRF bit is set.

Bit 0 = SBK Send break

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 62).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 62).

TIE TCIE RIE ILIE TE RE RWU1) SBK1)

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

Note: When LIN slave mode is disabled, the SCI-

BRR register controls the conventional baud rate

generator.

Bits 7:6 = SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and

SCP0 bits define the total division applied to the

bus clock to yield the transmit rate clock in conven-

tional Baud Rate Generator mode.

Bits 2:0 = SCR[2:0] SCI Receiver rate divider

These 3 bits, in conjunction with the SCP[1:0] bits

define the total division applied to the bus clock to

yield the receive rate clock in conventional Baud

Rate Generator mode.

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

PR Prescaling factor SCP1 SCP0

100

410

13 1

TR dividing factor SCT2 SCT1 SCT0

410

32 1

64 10

128 1

RR dividing factor SCR2 SCR1 SCR0

410

32 1

64 10

128 1

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)

EXTENDED RECEIVE PRESCALER DIVISION

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive

Prescaler Register

The extended Baud Rate Generator is activated

when a value other than 00h is stored in this regis-

ter. The clock frequency from the 16 divider (see

Figure 64) is divided by the binary factor set in the

SCIERPR register (in the range 1 to 255).

The extended baud rate generator is not active af-

ter a reset.

EXTENDED TRANSMIT PRESCALER DIVISION

Read/Write

Reset Value:0000 0000 (00h)

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit

Prescaler Register

The extended Baud Rate Generator is activated

when a value other than 00h is stored in this regis-

ter. The clock frequency from the 16 divider (see

Figure 64) is divided by the binary factor set in the

SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not active af-

ter a reset.

Note: In LIN slave mode, the Conventional and

Extended Baud Rate Generators are disabled.

ERPR

7ERPR

6ERPR

5ERPR

4ERPR

3ERPR

2ERPR

1ERPR

ETPR

7ETPR

6ETPR

5ETPR

4ETPR

3ETPR

2ETPR

1ETPR

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)

10.5.9 LIN Mode - Functional Description.

The block diagram of the Serial Control Interface,

in LIN slave mode is shown in Figure 66.

It uses six registers:

– 3 control registers: SCICR1, SCICR2 and

SCICR3

– 2 status registers: the SCISR register and the

LHLR register mapped at the SCIERPR address

– A baud rate register: LPR mapped at the SCI-

BRR address and an associated fraction register

LPFR mapped at the SCIETPR address

The bits dedicated to LIN are located in the

SCICR3. Refer to the register descriptions in Sec-

tion 10.5.10for the definitions of each bit.

10.5.9.1 Entering LIN Mode

To use the LINSCI in LIN mode the following con-

figuration must be set in SCICR3 register:

– Clear the M bit to configure 8-bit word length.

– Set the LINE bit.

Master

To enter master mode the LSLV bit must be reset

In this case, setting the SBK bit will send 13 low

bits.

Then the baud rate can programmed using the

SCIBRR, SCIERPR and SCIETPR registers.

In LIN master mode, the Conventional and / or Ex-

tended Prescaler define the baud rate (as in stand-

ard SCI mode)

Slave

Set the LSLV bit in the SCICR3 register to enter

LIN slave mode. In this case, setting the SBK bit

will have no effect.

In LIN Slave mode the LIN baud rate generator is

selected instead of the Conventional or Extended

Prescaler. The LIN baud rate generator is com-

mon to the transmitter and the receiver.

Then the baud rate can be programmed using

LPR and LPRF registers.

Note: It is mandatory to set the LIN configuration

first before programming LPR and LPRF, because

the LIN configuration uses a different baud rate

generator from the standard one.

10.5.9.2 LIN Transmission

In LIN mode the same procedure as in SCI mode

has to be applied for a LIN transmission.

To transmit the LIN Header the proceed as fol-

lows:

– First set the SBK bit in the SCICR2 register to

start transmitting a 13-bit LIN Synch Break

– reset the SBK bit

– Load the LIN Synch Field (0x55) in the SCIDR

– Wait until the SCIDR is empty (TDRE bit set in

the SCISR register)

– Load the LIN message Identifier in the SCIDR

1|\\\\|\ \ J j +|0+M2+\ir\ev E]

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

Figure 65. LIN Characters

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start

Bit Stop

Bit

Start

Bit

Idle Line Start

Bit

8-bit Word length (M bit is reset)

LIN Synch Break = 13 low bits Start

Bit

Extra

‘1’

Data Character

Next Data Character

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start

Bit Stop

Bit

Start

Bit

LIN Synch Field

Measurement for baud rate autosynchronization

¢i¢¢¢¢ SCICRS

ST7MC1xx/ST7MC2xx

124/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

Figure 66. SCI Block Diagram in LIN Slave Mode

WAKE

UNIT

RECEIVER

CONTROL

SCISR

TRANSMIT

CONTROL

TDRE TC RDRF IDLE OR/ NF FE PE

SCI

CONTROL

INTERRUPT

SCICR1

R8 T8 SCID M

WAKE

PCE PS PIE

Received Data Register (RDR)

Receive Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER) SCIDR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

CPU

/ LDIV

SBKRWURETEILIERIETCIETIE

SCICR2

LIN SLAVE BAUD RATE

AUTO SYNCHRONIZATION

CPU

SCICR3

LINE LASE LHIE LSFLHDF

EXTENDED PRESCALER

CONVENTIONAL BAUD RATE

GENERATOR

/16

SCIBRR

LPR7 LPR0

LIN SLAVE BAUD RATE GENERATOR

UNIT

LDUM LHDM

LHE

LSLV

lDlSlD361D4®ID5

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.3 LIN Reception

In LIN mode the reception of a byte is the same as

in SCI mode but the LINSCI has features for han-

dling the LIN Header automatically (identifier de-

tection) or semiautomatically (Synch Break detec-

tion) depending on the LIN Header detection

mode. The detection mode is selected by the

LHDM bit in the SCICR3.

Additionally, an automatic resynchronization fea-

ture can be activated to compensate for any clock

deviation, for more details please refer to Section

10.5.9.5 LIN Baud Rate.

LIN Header Handling by a Slave

Depending on the LIN Header detection method

the LINSCI will signal the detection of a LIN Head-

er after the LIN Synch Break or after the Identifier

has been successfully received.

Note:

It is recommended to combine the Header detec-

tion function with Mute mode. Putting the LINSCI

in Mute mode allows the detection of Headers only

and prevents the reception of any other charac-

ters.

This mode can be used to wait for the next Header

without being interrupted by the data bytes of the

current message in case this message is not rele-

vant for the application.

Synch Break Detection (LHDM = 0):

When a LIN Synch Break is received:

– The RDRF bit in the SCISR register is set. It in-

dicates that the content of the shift register is

transferred to the SCIDR register, a value of

0x00 is expected for a Break.

– The LHDF flag in the SCICR3 register indicates

that a LIN Synch Break Field has been detected.

– An interrupt is generated if the LHIE bit in the

SCICR3 register is set and the I[1:0] bits are

cleared in the CCR register.

– Then the LIN Synch Field is received and meas-

ured.

– If automatic resynchronization is enabled (LA-

SE bit = 1), the LIN Synch Field is not trans-

ferred to the shift register: There is no need to

clear the RDRF bit.

– If automatic resynchronization is disabled (LA-

SE bit = 0), the LIN Synch Field is received as

a normal character and transferred to the

SCIDR register and RDRF is set.

Note:

In LIN slave mode, the FE bit detects all frame er-

ror which does not correspond to a break.

Identifier Detection (LHDM = 1):

This case is the same as the previous one except

that the LHDF and the RDRF flags are set only af-

ter the entire header has been received (this is

true whether automatic resynchronization is ena-

bled or not). This indicates that the LIN Identifier is

available in the SCIDR register.

Notes:

During LIN Synch Field measurement, the SCI

state machine is switched off: No characters are

transferred to the data register.

LIN Slave parity

In LIN Slave mode (LINE and LSLV bits are set)

LIN parity checking can be enabled by setting the

PCE bit.

In this case, the parity bits of the LIN Identifier

Field are checked. The identifier character is rec-

ognized as the third received character after a

break character (included):

The bits involved are the two MSB positions (7th

and 8th bits if M = 0; 8th and 9th bits if M = 0) of

the identifier character. The check is performed as

specified by the LIN specification:

LIN Synch LIN Synch Identifier

parity bits

Field Field

Break

Identifier Field

parity bits

ID0

start bit stop bit

ID1 ID2 ID3 ID4 ID5 P0 P1

identifier bits

P1 ID1 ID3 ID4 ID5⊕⊕⊕=

P0 ID0=ID1 ID2 ID4⊕⊕⊕ M=0

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.4 LIN Error Detection

LIN Header Error Flag

The LIN Header Error Flag indicates that an invalid

LIN Header has been detected.

When a LIN Header Error occurs:

– The LHE flag is set

– An interrupt is generated if the RIE bit is set and

the I[1:0] bits are cleared in the CCR register.

If autosynchronization is enabled (LASE bit = 1),

this can mean that the LIN Synch Field is corrupt-

ed, and that the SCI is in a blocked state (LSF bit is

set). The only way to recover is to reset the LSF bit

and then to clear the LHE bit.

– The LHE bit is reset by an access to the SCISR

LHE/OVR Error Conditions

When Auto Resynchronization is disabled (LASE

bit = 0), the LHE flag detects:

– That the received LIN Synch Field is not equal to

55h.

– That an overrun occurred (as in standard SCI

mode)

– Furthermore, if LHDM is set it also detects that a

LIN Header Reception Timeout occurred (only if

LHDM is set).

When the LIN auto-resynchronization is enabled

(LASE bit = 1), the LHE flag detects:

– That the deviation error on the Synch Field is

outside the LIN specification which allows up to

+/-15.5% of period deviation between the slave

and master oscillators.

– A LIN Header Reception Timeout occurred.

If THEADER > THEADER_MAX then the LHE flag is

set. Refer to Figure 67. (only if LHDM is set to 1)

– An overflow during the Synch Field Measure-

ment, which leads to an overflow of the divider

registers. If LHE is set due to this error then the

SCI goes into a blocked state (LSF bit is set).

– That an overrun occurred on Fields other than

the Synch Field (as in standard SCI mode)

Deviation Error on the Synch Field

The deviation error is checking by comparing the

current baud rate (relative to the slave oscillator)

with the received LIN Synch Field (relative to the

master oscillator). Two checks are performed in

parallel:

– The first check is based on a measurement be-

tween the first falling edge and the last falling

edge of the Synch Field. Let us refer to this peri-

od deviation as D:

If the LHE flag is set, it means that:

D > 15.625%

If LHE flag is not set, it means that:

D < 16.40625%

If 15.625% ≤ D < 16.40625%, then the flag can

be either set or reset depending on the dephas-

ing between the signal on the RDI line and the

CPU clock.

– The second check is based on the measurement

of each bit time between both edges of the Synch

Field: this checks that each of these bit times is

large enough compared to the bit time of the cur-

rent baud rate.

When LHE is set due to this error then the SCI

goes into a blocked state (LSF bit is set).

LIN Header Time-out Error

When the LIN Identifier Field Detection Method is

used (by configuring LHDM to 1) or when LIN

auto-resynchronization is enabled (LASE bit = 1),

the LINSCI automatically monitors the

THEADER_MAX condition given by the LIN protocol.

If the entire Header (up to and including the STOP

bit of the LIN Identifier Field) is not received within

the maximum time limit of 57 bit times then a LIN

Header Error is signalled and the LHE bit is set in

the SCISR register.

Figure 67. LIN Header Reception Timeout

The time-out counter is enabled at each break de-

tection. It is stopped in the following conditions:

- A LIN Identifier Field has been received

- An LHE error occurred (other than a timeout er-

ror).

- A software reset of LSF bit (transition from high to

low) occurred during the analysis of the LIN Synch

Field or

If LHE bit is set due to this error during the LIN

Synchr Field (if LASE bit = 1) then the SCI goes

into a blocked state (LSF bit is set).

LIN Synch LIN Synch Identifier

Field Field

Break

THEADER

ll ‘ // ak H #MEMMW» 473—» E]

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

If LHE bit is set due to this error during Fields other

than LIN Synch Field or if LASE bit is reset then

the current received Header is discarded and the

SCI searches for a new Break Field.

Note on LIN Header Time-out Limit

According to the LIN specification, the maximum

length of a LIN Header which does not cause a

timeout is equal to 1.4 * (34 + 1) = 49

TBIT_MASTER.

TBIT_MASTER refers to the master baud rate.

When checking this timeout, the slave node is de-

synchronized for the reception of the LIN Break

and Synch fields. Consequently, a margin must be

allowed, taking into account the worst case: This

occurs when the LIN identifier lasts exactly 10

TBIT_MASTER periods. In this case, the LIN Break

and Synch fields last 49 - 10 = 39TBIT_MASTER pe-

riods.

Assuming the slave measures these first 39 bits

with a desynchronized clock of 15.5%. This leads

to a maximum allowed Header Length of:

39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER

= 56.15 TBIT_SLAVE

A margin is provided so that the time-out occurs

when the header length is greater than 57

TBIT_SLAVE periods. If it is less than or equal to 57

TBIT_SLAVE periods, then no timeout occurs.

LIN Header Length

Even if no timeout occurs on the LIN Header, it is

possible to have access to the effective LIN head-

er Length (THEADER) through the LHL register.

This allows monitoring at software level the

TFRAME_MAX condition given by the LIN protocol.

This feature is only available when LHDM bit = 1

or when LASE bit = 1.

Mute Mode and Errors

In mute mode when LHDM bit = 1, if an LHE error

occurs during the analysis of the LIN Synch Field

or if a LIN Header Time-out occurs then the LHE

bit is set but it does not wake up from mute mode.

In this case, the current header analysis is discard-

ed. If needed, the software has to reset LSF bit.

Then the SCI searches for a new LIN header.

In mute mode, if a framing error occurs on a data

(which is not a break), it is discarded and the FE bit

is not set.

When LHDM bit = 1, any LIN header which re-

spects the following conditions causes a wake-up

from mute mode:

- A valid LIN Break Field (at least 11 dominant bits

followed by a recessive bit)

- A valid LIN Synch Field (without deviation error)

- A LIN Identifier Field without framing error. Note

that a LIN parity error on the LIN Identifier Field

does not prevent wake-up from mute mode.

- No LIN Header Time-out should occur during

Header reception.

Figure 68. LIN Synch Field Measurement

LIN Synch Break

Extra

’1’ Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start

Bit Stop

Bit

Start

Bit

LIN Synch Field

Measurement = 8.TBR = SM.tCPU

LPR(n) LPR(n+1)

LPR = tBR / (16.tCPU) = Rounding (SM / 128)

tCPU = CPU period

tBR = Baud Rate period

tBR = 16.LP.tCPU

SM = Synch Measurement Register (15 bits)

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.5 LIN Baud Rate

Baud rate programming is done by writing a value

in the LPR prescaler or performing an automatic

resynchronization as described below.

Automatic Resynchronization

To automatically adjust the baud rate based on

measurement of the LIN Synch Field:

– Write the nominal LIN Prescaler value (usually

depending on the nominal baud rate) in the

LPFR / LPR registers.

– Set the LASE bit to enable the Auto Synchroni-

zation Unit.

When Auto Synchronization is enabled, after each

LIN Synch Break, the time duration between five

falling edges on RDI is sampled on fCPU and the

result of this measurement is stored in an internal

15-bit register called SM (not user accessible)

(See Figure 68). Then the LDIV value (and its as-

sociated LPFR and LPR registers) are automati-

cally updated at the end of the fifth falling edge.

During LIN Synch field measurement, the SCI

state machine is stopped and no data is trans-

ferred to the data register.

10.5.9.6 LIN Slave Baud Rate Generation

In LIN mode, transmission and reception are driv-

en by the LIN baud rate generator

Note: LIN Master mode uses the Extended or

Conventional prescaler register to generate the

baud rate.

If LINE bit = 1 and LSLV bit = 1 then the Conven-

tional and Extended Baud Rate Generators are

disabled: the baud rate for the receiver and trans-

mitter are both set to the same value, depending

on the LIN Slave baud rate generator:

with:

LDIV is an unsigned fixed point number. The man-

tissa is coded on 8 bits in the LPR register and the

fraction is coded on 4 bits in the LPFR register.

If LASE bit = 1 then LDIV is automatically updated

at the end of each LIN Synch Field.

Three registers are used internally to manage the

auto-update of the LIN divider (LDIV):

- LDIV_NOM (nominal value written by software at

LPR/LPFR addresses)

- LDIV_MEAS (results of the Field Synch meas-

urement)

- LDIV (used to generate the local baud rate)

The control and interactions of these registers is

explained in Figure 69 and Figure 70. It depends

on the LDUM bit setting (LIN Divider Update Meth-

od)

Note:

As explained in Figure 69 and Figure 70, LDIV

can be updated by two concurrent actions: a

transfer from LDIV_MEAS at the end of the LIN

Sync Field and a transfer from LDIV_NOM due

to a software write of LPR. If both operations

occur at the same time, the transfer from

LDIV_NOM has priority.

Tx = Rx =

(16*LDIV)

fCPU

LPR Wme LPFR MA Update ak end of nch Fie‘d / / Wme LPFR Update ak end of nch Fie‘d

ST7MC1xx/ST7MC2xx

129/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

Figure 69. LDIV Read / Write Operations When LDUM = 0

Figure 70. LDIV Read / Write Operations When LDUM = 1

MANT(7:0) LDIV

FRAC(3:0)

LDIV_NOM

Baud Rate

Read LPR

Write LPFR

Update

at end of

Synch Field

FRAC(3:0) MANT(7:0)

LDIV_MEAS

FRAC(3:0) MANT(7:0)

Write LPR

Read LPFR

Generation

LIN Sync Field

Measurement

Write LPR

MANT(7:0) LDIV

FRAC(3:0)

LDIV_NOM

Baud Rate

Read LPR

Write LPFR

Update

RDRF = 1

at end of

Synch Field

FRAC(3:0) MANT(7:0)

LDIV_MEAS

FRAC(3:0) MANT(7:0)

Write LPR

Read LPFR

Generation

LIN Sync Field

Measurement

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.7 LINSCI Clock Tolerance

LINSCI Clock Tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no

characters have been transmitted for a relatively

long time), the maximum tolerated deviation of the

LINSCI clock is +/-15%.

If the deviation is within this range then the LIN

Synch Break is detected properly when a new re-

ception occurs.

This is made possible by the fact that masters

send 13 low bits for the LIN Synch Break, which

can be interpreted as 11 low bits (13 bits -15% =

11.05) by a “fast” slave and then considered as a

LIN Synch Break. According to the LIN specifica-

tion, a LIN Synch Break is valid when its duration

is greater than tSBRKTS = 10. This means that the

LIN Synch Break must last at least 11 low bits.

Note: If the period desynchronization of the slave

is +15% (slave too slow), the character “00h”

which represents a sequence of 9 low bits must

not be interpreted as a break character (9 bits +

15% = 10.35). Consequently, a valid LIN Synch

break must last at least 11 low bits.

LINSCI Clock Tolerance when Synchronized

When synchronization has been performed, fol-

lowing reception of a LIN Synch Break, the LINS-

CI, in LIN mode, has the same clock deviation tol-

erance as in SCI mode, which is explained below:

During reception, each bit is oversampled 16

times. The mean of the 8th, 9th and 10th samples

is considered as the bit value.

Consequently, the clock frequency should not vary

more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start

bit, so that when receiving 10 bits (one start bit, 1

data byte, 1 stop bit), the clock deviation should

not exceed 3.75%.

10.5.9.8 Clock Deviation Causes

The causes which contribute to the total deviation

are:

–D

TRA: Deviation due to transmitter error.

Note: The transmitter can be either a master

or a slave (in case of a slave listening to the

response of another slave).

–D

MEAS: Error due to the LIN Synch measure-

ment performed by the receiver.

–D

QUANT: Error due to the baud rate quantiza-

tion of the receiver.

–D

REC: Deviation of the local oscillator of the

receiver: This deviation can occur during the

reception of one complete LIN message as-

suming that the deviation has been compen-

sated at the beginning of the message.

–D

TCL: Deviation due to the transmission line

(generally due to the transceivers)

All the deviations of the system should be added

and compared to the LINSCI clock tolerance:

DTRA + DMEAS +DQUANT + DREC + DTCL < 3.75%

Figure 71.Bit Sampling in Reception Mode

RDI LINE

Sample

clock 1234567891011

12 13 14 15 16

sampled values

One bit time

6/16

7/16 7/16

ST7MC1xx/ST7MC2xx

131/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.9.9 Error due to LIN Synch measurement

The LIN Synch Field is measured over eight bit

times.

This measurement is performed using a counter

clocked by the CPU clock. The edge detections

are performed using the CPU clock cycle.

This leads to a precision of 2 CPU clock cycles for

the measurement which lasts 16*8*LDIV clock cy-

cles.

Consequently, this error (DMEAS) is equal to:

2 / (128*LDIVMIN).

LDIVMIN corresponds to the minimum LIN prescal-

er content, leading to the maximum baud rate, tak-

ing into account the maximum deviation of +/-15%.

10.5.9.10 Error due to Baud Rate Quantization

The baud rate can be adjusted in steps of 1 / (16 *

LDIV). The worst case occurs when the “real”

baud rate is in the middle of the step.

This leads to a quantization error (DQUANT) equal

to 1 / (2*16*LDIVMIN).

10.5.9.11 Impact of Clock Deviation on

Maximum Baud Rate

The choice of the nominal baud rate (LDIVNOM)

will influence both the quantization error (DQUANT)

and the measurement error (DMEAS). The worst

case occurs for LDIVMIN.

Consequently, at a given CPU frequency, the

maximum possible nominal baud rate (LPRMIN)

should be chosen with respect to the maximum tol-

erated deviation given by the equation:

DTRA + 2 / (128*LDIVMIN) + 1 / (2*16*LDIVMIN)

+ DREC + DTCL < 3.75%

Example:

A nominal baud rate of 20Kbits/s at TCPU = 125ns

(8 MHz) leads to LDIVNOM = 25d.

LDIVMIN = 25 - 0.15*25 = 21.25

DMEAS = 2 / (128*LDIVMIN) * 100 = 0.00073%

DQUANT = 1 / (2*16*LDIVMIN) * 100 = 0.0015%

LIN Slave systems

For LIN Slave systems (the LINE and LSLV bits

are set), receivers wake up by LIN Synch Break or

LIN Identifier detection (depending on the LHDM

bit).

Hot Plugging Feature for LIN Slave Nodes

In LIN Slave Mute Mode (the LINE, LSLV and

RWU bits are set) it is possible to hot plug to a net-

work during an ongoing communication flow. In

this case the SCI monitors the bus on the RDI line

until 11 consecutive dominant bits have been de-

tected and discards all the other bits received.

ST7MC1xx/ST7MC2xx

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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

10.5.10 LIN Mode Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bits 7:4 = Same function as in SCI mode, please

refer to Section 10.5.8 SCI Mode Register De-

scription.

Bit 3 = LHE LIN Header Error.

During LIN Header this bit signals three error

types:

– The LIN Synch Field is corrupted and the SCI is

blocked in LIN Synch State (LSF bit = 1).

– A timeout occurred during LIN Header reception

– An overrun error was detected on one of the

header field (see OR bit description in Section

10.5.8 SCI Mode Register Description)).

An interrupt is generated if RIE = 1 in the SCICR2

bit must first be reset (to exit LIN Synch Field state

and then to be able to clear LHE flag). Then it is

cleared by the following software sequence: An

access to the SCISR register followed by a read to

the SCIDR register.

0: No LIN Header error

1: LIN Header error detected

Note:

Apart from the LIN Header this bit signals an Over-

run Error as in SCI mode, (see description in Sec-

tion 10.5.8 SCI Mode Register Description)

Bit 2 = NF Noise flag

In LIN Master mode (LINE bit = 1 and LSLV bit = 0)

this bit has the same function as in SCI mode,

please refer to Section 10.5.8 SCI Mode Register

Description

In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)

this bit has no meaning.

Bit 1 = FE Framing error.

In LIN slave mode, this bit is set only when a real

framing error is detected (if the stop bit is dominant

(0) and at least one of the other bits is recessive

(1). It is not set when a break occurs, the LHDF bit

is used instead as a break flag (if the LHDM

bit = 0). It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error

1: Framing error detected

Bit 0 = PE Parity error.

This bit is set by hardware when a LIN parity error

occurs (if the PCE bit is set) in receiver mode. It is

cleared by a software sequence (a read to the sta-

tus register followed by an access to the SCIDR

data register). An interrupt is generated if PIE = 1

in the SCICR1 register.

0: No LIN parity error

1: LIN Parity error detected

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

Bits 7:3 = Same function as in SCI mode, please

refer to Section 10.5.8 SCI Mode Register De-

scription.

Bit 2 = PCE Parity control enable.

This bit is set and cleared by software. It selects

the hardware parity control for LIN identifier parity

check.

0: Parity control disabled

1: Parity control enabled

When a parity error occurs, the PE bit in the

SCISR register is set.

Bit 1 = Reserved

Bit 0 = Same function as in SCI mode, please refer

to Section 10.5.8 SCI Mode Register Description.

TDRE TC RDRF IDLE LHE NF FE PE

R8 T8 SCID M WAKE PCE PS PIE

ST7MC1xx/ST7MC2xx

133/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:2 Same function as in SCI mode, please re-

fer to Section 10.5.8 SCI Mode Register Descrip-

tion.

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

Notes:

– Mute mode is recommended for detecting only

the Header and avoiding the reception of any

other characters. For more details please refer to

Section 10.5.9.3 LIN Reception.

– In LIN slave mode, when RDRF is set, the soft-

ware can not set or clear the RWU bit.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

CONTROL REGISTER 3 (SCICR3)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = LDUM LIN Divider Update Method.

This bit is set and cleared by software and is also

cleared by hardware (when RDRF = 1). It is only

used in LIN Slave mode. It determines how the LIN

Divider can be updated by software.

0: LDIV is updated as soon as LPR is written (if no

Auto Synchronization update occurs at the

same time).

1: LDIV is updated at the next received character

(when RDRF = 1) after a write to the LPR regis-

ter

Notes:

- If no write to LPR is performed between the set-

ting of LDUM bit and the reception of the next

character, LDIV will be updated with the old value.

- After LDUM has been set, it is possible to reset

the LDUM bit by software. In this case, LDIV can

be modified by writing into LPR / LPFR registers.

Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.

These bits configure the LIN mode:

The LIN Master configuration enables:

The capability to send LIN Synch Breaks (13 low

bits) using the SBK bit in the SCICR2 register.

The LIN Slave configuration enables:

– The LIN Slave Baud Rate generator. The LIN

Divider (LDIV) is then represented by the LPR

and LPFR registers. The LPR and LPFR reg-

isters are read/write accessible at the address

of the SCIBRR register and the address of the

SCIETPR register

– Management of LIN Headers.

– LIN Synch Break detection (11-bit dominant).

– LIN Wake-Up method (see LHDM bit) instead

of the normal SCI Wake-Up method.

– Inhibition of Break transmission capability

(SBK has no effect)

– LIN Parity Checking (in conjunction with the

PCE bit)

Bit 4 = LASE LIN Auto Synch Enable.

This bit enables the Auto Synch Unit (ASU). It is

set and cleared by software. It is only usable in LIN

Slave mode.

0: Auto Synch Unit disabled

1: Auto Synch Unit enabled.

Bit 3 = LHDM LIN Header Detection Method

This bit is set and cleared by software. It is only us-

able in LIN Slave mode. It enables the Header De-

tection Method. In addition if the RWU bit in the

TIE TCIE RIE ILIE TE RE RWU SBK

LDUM LINE LSLV LASE LHDM LHIE LHDF LSF

LINE LSLV Meaning

0 x LIN mode disabled

10 LIN Master Mode

1 LIN Slave Mode

ST7MC1xx/ST7MC2xx

134/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

SCICR2 register is set, the LHDM bit selects the

Wake-Up method (replacing the WAKE bit).

0: LIN Synch Break Detection Method

1: LIN Identifier Field Detection Method

Bit 2 = LHIE LIN Header Interrupt Enable

This bit is set and cleared by software. It is only us-

able in LIN Slave mode.

0: LIN Header Interrupt is inhibited.

1: An SCI interrupt is generated whenever

LHDF = 1.

Bit 1 = LHDF LIN Header Detection Flag

This bit is set by hardware when a LIN Header is

detected and cleared by a software sequence (an

access to the SCISR register followed by a read of

the SCICR3 register). It is only usable in LIN Slave

mode.

0: No LIN Header detected.

1: LIN Header detected.

Notes: The header detection method depends on

the LHDM bit:

– If LHDM = 0, a header is detected as a LIN

Synch Break.

– If LHDM = 1, a header is detected as a LIN

Identifier, meaning that a LIN Synch Break

Field + a LIN Synch Field + a LIN Identifier

Field have been consecutively received.

Bit 0 = LSF LIN Synch Field State

This bit indicates that the LIN Synch Field is being

analyzed. It is only used in LIN Slave mode. In

Auto Synchronization Mode (LASE bit = 1), when

the SCI is in the LIN Synch Field State it waits or

counts the falling edges on the RDI line.

It is set by hardware as soon as a LIN Synch Break

is detected and cleared by hardware when the LIN

Synch Field analysis is finished (See Figure 72).

This bit can also be cleared by software to exit LIN

Synch State and return to idle mode.

0: The current character is not the LIN Synch Field

1: LIN Synch Field State (LIN Synch Field under-

going analysis)

Figure 72. LSF Bit Set and Clear

LIN DIVIDER REGISTERS

LDIV is coded using the two registers LPR and LP-

FR. In LIN Slave mode, the LPR register is acces-

sible at the address of the SCIBRR register and

the LPFR register is accessible at the address of

the SCIETPR register.

LIN PRESCALER REGISTER (LPR)

Read/Write

Reset Value: 0000 0000 (00h)

LPR[7:0] LIN Prescaler (mantissa of LDIV)

These 8 bits define the value of the mantissa of the

LIN Divider (LDIV):

Caution: LPR and LPFR registers have different

meanings when reading or writing to them. Conse-

quently bit manipulation instructions (BRES or

BSET) should never be used to modify the

LPR[7:0] bits, or the LPFR[3:0] bits.

LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0

LPR[7:0] Rounded Mantissa (LDIV)

00h SCI clock disabled

01h 1

... ...

FEh 254

FFh 255

LIN Synch LIN Synch Identifier

parity bits

Field Field

Break

11 dominant bits

LSF bit

ST7MC1xx/ST7MC2xx

135/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

LIN PRESCALER FRACTION REGISTER

(LPFR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:4 = Reserved.

Bits 3:0 = LPFR[3:0] Fraction of LDIV

These 4 bits define the fraction of the LIN Divider

(LDIV):

1. When initializing LDIV, the LPFR register must

be written first. Then, the write to the LPR register

will effectively update LDIV and so the clock gen-

eration.

2. In LIN Slave mode, if the LPR[7:0] register is

equal to 00h, the transceiver and receiver input

clocks are switched off.

Examples of LDIV coding:

Example 1: LPR = 27d and LPFR = 12d

This leads to:

Mantissa (LDIV) = 27d

Fraction (LDIV) = 12/16 = 0.75d

Therefore LDIV = 27.75d

Example 2: LDIV = 25.62d

This leads to:

LPFR = rounded(16*0.62d)

= rounded(9.92d) = 10d = Ah

LPR = mantissa (25.620d) = 25d = 1Bh

Example 3: LDIV = 25.99d

This leads to:

LPFR = rounded(16*0.99d)

= rounded(15.84d) = 16d

0000

LPFR

LPFR[3:0] Fraction (LDIV)

0h 0

1h 1/16

... ...

Eh 14/16

Fh 15/16

HEADER HEADER HEADER

ST7MC1xx/ST7MC2xx

136/309

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)

LIN HEADER LENGTH REGISTER (LHLR)

Read Only

Reset Value: 0000 0000 (00h).

Note: In LIN Slave mode when LASE = 1 or LHDM

= 1, the LHLR register is accessible at the address

of the SCIERPR register.

Otherwise this register is always read as 00h.

Bits 7:0 = LHL[7:0] LIN Header Length.

This is a read-only register, which is updated by

hardware if one of the following conditions occurs:

- After each break detection, it is loaded with

“FFh”.

- If a timeout occurs on THEADER, it is loaded with

00h.

- After every successful LIN Header reception (at

the same time than the setting of LHDF bit), it is

loaded with a value (LHL) which gives access to

the number of bit times of the LIN header length

(THEADER). The coding of this value is explained

below:

LHL Coding:

THEADER_MAX = 57

LHL(7:2) represents the mantissa of (57 - THEAD-

ER)

LHL(1:0) represents the fraction (57 - THEADER)

Example of LHL coding:

Example 1: LHL = 33h = 001100 11b

LHL(7:3) = 1100b = 12d

LHL(1:0) = 11b = 3d

This leads to:

Mantissa (57 - THEADER) = 12d

Fraction (57 - THEADER) = 3/4 = 0.75

Therefore:

(57 - THEADER) = 12.75d

and THEADER = 44.25d

Example 2:

57 - THEADER = 36.21d

LHL(1:0) = rounded(4*0.21d) = 1d

LHL(7:2) = Mantissa (36.21d) = 36d = 24h

Therefore LHL(7:0) = 10010001 = 91h

Example 3:

57 - THEADER = 36.90d

LHL(1:0) = rounded(4*0.90d) = 4d

The carry must be propagated to the matissa:

LHL(7:2) = Mantissa (36.90d) + 1 = 37d =

Therefore LHL(7:0) = 10110000 = A0h

LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0

LHL[7:2] Mantissa

(57 - THEADER)

Mantissa

(THEADER)

0h 0 57

1h 1 56

... ... ...

39h 56 1

3Ah 57 0

3Bh 58 Never Occurs

... ... ...

3Eh 62 Never Occurs

3Fh 63 Initial value

LHL[1:0] Fraction (57 - THEADER)

0h 0

1h 1/4

2h 1/2

3h 3/4

ST7MC1xx/ST7MC2xx

137/309

SERIAL COMMUNICATION INTERFACE (Cont’d)

Table 21. SCI Register Map and Reset Values

Addr.

(Hex.) Register Name 7 6 5 4 3 2 1 0

0018h SCI1SR

Reset Value

TDRE

RDRF

IDLE

OR/LHE

0019h SCI1DR

Reset Value

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

001Ah

SCI1BRR

LPR (LIN Slave Mode)

Reset Value

SCP1

LPR7

SCP0

LPR6

SCT2

LPR5

SCT1

LPR4

SCT0

LPR3

SCR2

LPR2

SCR1

LPR1

SCR0

LPR0

001Bh SCI1CR1

Reset Value

SCID

WAKE

PCE

PIE

001Ch SCI1CR2

Reset Value

TIE

TCIE

RIE

ILIE

RWU

SBK

001Dh SCI1CR3

Reset Value

LDUM

LINE

LSLV

LASE

LHDM

LHIE

LHDF

LSF

001Eh

SCI1ERPR

LHLR (LIN Slave Mode)

Reset Value

ERPR7

LHL7

ERPR6

LHL6

ERPR5

LHL5

ERPR4

LHL4

ERPR3

LHL3

ERPR2

LHL2

ERPR1

LHL1

ERPR0

LHL0

001Fh

SCI1TPR

LPRF (LIN Slave Mode)

Reset Value

ETPR7

ETPR6

ETPR5

ETPR4

ETPR3

LPRF3

ETPR2

LPRF2

ETPR1

LPRF1

ETPR0

LPRF0

ST7MC1xx/ST7MC2xx

138/309

10.6 MOTOR CONTROLLER (MTC)

10.6.1 Introduction

The ST7 Motor Controller (MTC) can be seen as a

Three-Phase Pulse Width Modulator multiplexed

on six output channels and a Back Electromotive

Force (BEMF) zero-crossing detector for sensor-

less control of Permanent Magnet Direct Current

(PM BLDC) brushless motors.

The MTC is particularly suited to driving brushless

motors (either induction or permanent magnet

types) and supports operating modes like:

– Commutation step control with motor voltage

regulation and current limitation

– Commutation step control with motor current

regulation, i.e. direct torque control

– Position Sensor or sensorless motor phase com-

mutation control (six-step mode)

– BEMF zero-crossing detection with high sensitiv-

ity. The integrated phase voltage comparator is

directly referred to the full BEMF voltage without

any attenuation. A BEMF voltage down to

200 mV can be detected, providing high noise

immunity and self-commutated operation in a

large speed range.

– Realtime motor winding demagnetization detec-

tion for fine-tuning the phase voltage masking

time to be applied before BEMF monitoring.

– Automatic and programmable delay between

BEMF zero-crossing detection and motor phase

commutation.

– PWM generation for three-phase sinewave or

three-channel independent PWM signals.

Table 22. MTC Functional Blocks

Section Page

Input Detection Block 146

Input Pins 146

Sensorless Mode 149

D Event detection 150

Z Event Detection 151

Demagnetization (D) Event 153

Z Event Generation (BEMF Zero Crossing) 155

Protection for ZH event detection 157

Position Sensor Mode 158

Sampling block 159

Commutation Noise Filter 162

Speed Sensor Mode 164

Tachogenerator Mode 164

Encoder Mode 165

Summary 166

Delay Manager 168

Switched Mode 169

Autoswitched Mode 171

Debug Option 172

Checks and Controls for simulated events 175

Speed Measurement Mode 180

Summary 185

PWM Manager 185

Voltage Mode 185

Over Current Handling in Voltage mode 186

Current Mode 186

Current Feedback Comparator 186

Current feedback amplifier 188

Measurement Window 188

Channel Manager 190

MPHST Phase State Register 191

Emergency Feature 191

Dead Time Generator 194

Programmable Chopper 199

PWM Generator Block 200

Main Features 200

Functional Description 201

Prescaler 201

PWM Operating mode 201

Repetition Down-Counter 205

PWM interrupt generation 205

Timer Re-synchronisation 206

PWM generator initialization and start-up 206

ST7MC1xx/ST7MC2xx

139/309

MOTOR CONTROLLER (Cont’d)

Table 23. MTC Registers 10.6.2 Main Features

■Two on-chip analog comparators, one for BEMF

zero-crossing detection, the other for current

regulation or limitation

■Seven selectable reference voltages for the

hysteresis comparator (0.2 V, 0.6 V, 1 V, 1.5 V,

2 V, 2.5 V, 3.5 V) and the possibility to select an

external reference pin (MCVREF).

■8-bit timer (MTIM) with three compare registers

and two capture features, which may be used as

the Delay manager of a speed measurement

unit

■Measurement window generator for BEMF

zero-crossing detection

■Filter option for the zero-crossing detection.

■Auto-calibrated prescaler with 16 division steps

■8x8-bit multiplier

■Phase input multiplexer

■Sophisticated output management:

– The six output channels can be split into two

groups (high & low)

– The PWM signal can be multiplexed on high,

low or both groups, alternatively or simultane-

ously, for six-step motor drives

– 12-bit PWM generator with full modulation ca-

pability (0 and 100% duty cycle), edge or cent-

er-aligned patterns

– Dedicated interrupt for PWM duty cycles up-

dating and associated PWM repetition coun-

ter.

– Programmable deadtime insertion unit.

– Programmable High frequency Chopper in-

sertion and high current PWM outputs for di-

rect optocoupler drives.

– The output polarity is programmable channel

by channel.

– A programmable bit (active low) forces the

outputs in HiZ, Low or High state, depending

on option byte 1 (refer to “ST7FMC Device

Configuration And Ordering Information” sec-

tion).

– An “emergency stop” input pin (active low)

asynchronously forces the outputs in HiZ, Low

or High state, depending on option byte 1 (re-

fer to “ST7FMC Device Configuration And Or-

dering Information” section).

page

(RPGS

bit)

Page

MTIM Timer Counter Register 0 207

MTIML Timer LSB (mode depend-

ent) 0207

MZPRV Capture Zn-1 Register 0 207

MZREG Capture Zn Register 0 207

MCOMP Compare Cn+1 Register 0 207

MDREG Demagnetization Reg. 0 207

MWGHT An Weight Register 0 208

MPRSR Prescaler & Sampling Reg. 0 208

MIMR Interrupt Mask Register 0 208

MISR Interrupt Status Register 0 209

MCRA Control Register A 0 210

MCRB Control Register B 0 212

MCRC Control Register C 0 213

MPHST Phase State Register 0 214

MDFR D Event Filter Register 0 216

MCFR Current Feedback Filter

MREF Reference register 0 217

MPCR PWM Control Register 0 218

MREP Repetition Counter Reg. 0 219

MCPWH Compare W Register High 0 219

MCPWL Compare W Register Low 0 219

MCPVH Compare V Register High 0 219

MCPVL Compare V Register Low 0 219

MCPUH Compare U Register High 0 220

MCPUL Compare U Register Low 0 220

MCP0H Compare 0 Register High 0 220

MCP0L Compare 0 Register Low 0 220

MDTG Dead Time Generator reg. 1 221

MPOL Polarity Register 1 222

MPWME PWM register 1 223

MCONF Configuration register 1 224

MPAR Parity register 1 225

MZFR Z Event Filter Register 1 226

MSCR Sampling Clock Register 1 227

ST7MC1xx/ST7MC2xx

140/309

MOTOR CONTROLLER (Cont’d)

10.6.3 Application Example: PM BLDC motor

drive

This example shows a six-step command se-

quence for a 3-phase permanent magnet DC

brushless motor (PM BLDC motor). Figure 74

shows the phase steps and voltage, while Table

24 shows the relevant phase configurations.

To run this kind of motor efficiently, an autoswitch-

ing mode has to be used, i.e. the position of the ro-

tor must self-generate the powered winding com-

mutation. The BEMF zero crossing (Z event) on

the non-excited winding is used by the MTC as a

rotor position sensor. The delay between this

event and the commutation is computed by the

MTC and the hardware commutation event Cn is

automatically generated after this delay.

After the commutation occurs, the MTC waits until

the winding is completely demagnetized by the

free-wheeling diode: during this phase the winding

is tied to 0V or to the HV high voltage rail and no

BEMF can be read. At the end of this phase a new

BEMF zero-crossing detection is enabled.

The end of demagnetization event (D), is also de-

tected by the MTC or simulated with a timer com-

pare feature when no detection is possible.

The MTC manages these three events always in

the same order: Z generates C after a delay com-

puted in realtime, then waits for D in order to ena-

ble the peripheral to detect another Z event.

The BEMF zero-crossing event (Z), can also be

detected by the MTC or simulated with a timer

compare feature when no detection is possible.

The speed regulation is managed by the micro-

controller, by means of an adjustable reference

current level in case of current control, or by direct

PWM duty-cycle adjustment in case of voltage

control.

IIIIIIIIHIHHHI IIf E]

ST7MC1xx/ST7MC2xx

141/309

MOTOR CONTROLLER (Cont’d)

Figure 73. Chronogram of Events (in Autoswitched Mode)

CH event

ZH or ZS event

Cn processing

Wait for Cn

Wait for Dn

DH event

DS event

Wait for Z

VDD

VSS

P signal when sampled

(Output of the

VREF

(Threshold value for

Voltage on phase A

Voltage on phase B

Voltage on phase C

analog MUX)

Input comparator)

BEMF

sampling

CH event

ZH or ZS event

Cn processing

Wait for Cn

Wait for Dn

DH event

DS event

Wait for Z

VDD

VSS

P signal when sampled

(Output of the

VREF

(Threshold value for

Voltage on phase A

Voltage on phase B

Voltage on phase C

analog MUX)

Input comparator)

BEMF

sampling

0‘ \ ‘ Demagneuzauon W Commutation delay 4—>I am lor BEMF = 0

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 74. Example of Command Sequence for 6-step Mode (typical 3-phase PM BLDC Motor

Control)

Node

Step Σ1Σ2Σ3Σ4Σ5Σ6Σ1Σ2Σ3

HV/2

Demagnetization

C2C4

D5Z5

Σ2Σ3Σ4Σ5

Commutation delay

Wait for BEMF = 0

HV/2

Note: Control & sampling PWM influence is not represented on these simplified chronograms.

Switch

Σ1Σ6

PWM off pulses

(BEMF induced by rotor)

Superimposed voltage

- approx. HV/2 (PWM on)

- approx. 0V (PWM off)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

All detections of Zn events are done during a short

measurement window while the high side switch is

turned off. For this reason the PWM signal is ap-

plied on the high side switches.

When the high side switch is off, the high side

winding is tied to 0V by the free-wheeling diode,

the low side winding voltage is also held at 0V by

the low side ON switch and the complete BEMF

voltage is present on the third winding: detection is

then possible.

Table 24. Step Configuration Summary

For a detailed description of the MTC registers,

see Section 10.6.13.

10.6.4 Application Example: AC Induction

Motor Drive

Although the command sequence is rather differ-

ent between a PM BLDC and an AC three-phase

induction motor, the Motor Controller can be con-

figured to generate three-phase sinusoidal voltag-

es.

A timer with three independent PWM channels is

available for this purpose. Based on each of the

PWM reference signal, two complemented PWM

signals with deadtime are generated on the output

pins (6 in total), to drive directly an inverter with tri-

ple half bridge topology.

The variable voltage levels to be applied on the

motor terminals come from continuously varying

duty cycle, from one PWM period to the other (re-

fer to Figure 75 on page 144). The PWM counter

generates a dedicated Update event (U event)

which:

– updates automatically the compare registers set-

ting the duty cycle to avoid time critical issues

and ensure glitchless PWM operation.

– generates a dedicated U interrupt in which the

values for the next coming update event are

loaded in compare preload registers.

The shape of the output voltage (voltage, frequen-

cy, sinewave, trapezoid, ...) is completely man-

aged by the applicative software, in charge of

computing the compare values to be loaded for a

given PWM duty-cycle (refer to Figure 76).

Configuration Step

Σ1Σ2Σ3Σ4Σ5Σ6

Phase state

Current direction A to B A to C B to C B to A C to A C to B

High side T0 T0 T2 T2 T4 T4

Low side T3 T5 T5 T1 T1 T3

OO[5:0] bits in MPHST register 001001 100001 100100 000110 010010 011000

BEMF

input

Measurement done on: MCIC MCIB MCIA MCIC MCIB MCIA

IS[1:0] bits in MPHST register 10 01 00 10 01 00

BEMF

edge

Back EMF shape Falling Rising Falling Rising Falling Rising

CPB bit in MCRB register

(ZVD bit = 0) 010101

Hardware or

Hardware-simulated

demagnetization

Voltage on measured point at the

start of demagnetization 0V HV 0V HV 0V HV

HDM-SDM bits in MCRB register 10 11 10 11 10 11

Demagnetization

switch

PWM side selection to accelerate

demagnetization Low Side High Side Low Side High Side Low Side High Side

Driver selection to accelerate de-

magnetization T3 T0 T5 T2 T1 T4

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Finally, the PWM modulated voltage generated by

the power stage is smoothed by the motor induct-

ance to get sinusoidal currents in the stator wind-

ings.

The induction motor being asynchronous, there is

no need to synchronize the rotor position to the

sinewave generation phase in most of the applica-

tions.

Part of the MTC dedicated to delay computation

and event sampling can thus be reconfigured to

perform speed acquisition of the most common

speed sensor, without the need of an additional

standard timer.

This speed measurement timer with clear-on-cap-

ture and clock prescaler auto-setting allows to

keep the CPU load to a minimum level while taking

benefit of the embedded input comparator and

edge detector.

Figure 75. Complementary PWM generation for three-phase induction motor (1 phase represented)

U event

Compare preload

MCP0

MCPU

PWM generator

counter

PWM Ref

Signal

MCO1

MCO0

Dead time

insertion

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 76. Typical command signals of a three-phase induction motor

Phase A *

Phase B *

Phase C *

* These simplified chronograms represent the phase voltages after low-pass filtering of the

PWM outputs reference signals

1% 0% 1%

PWM output

Duty Cycle

PWM output

PWM

51% 50% 49%

period

Duty Cycle

PWM output

Duty Cycle 99% 100% 99%99% 99%

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.5 Functional Description

The MTC can be split into five main parts as

shown in the simplified block diagram in Figure 77.

Each of these parts may be configured for different

purposes:

■INPUT DETECTION BLOCK with a comparator,

an input multiplexer and an incremental encoder

interface, which may work as:

– A BEMF zero-crossing detector

– A Speed Sensor Interface

■The DELAY MANAGER with an 8/16-bit timer

and an 8x8 bit multiplier, which may work as a:

– 8-bit delay manager

– Speed Measurement unit

■The PWM MANAGER, including a

measurement window generator, a mode

selector and a current comparator.

■The CHANNEL MANAGER with the PWM

multiplexer, polarity programming, deadtime

insertion and high frequency chopping

capability and emergency HiZ configuration

input.

■The THREE-PHASE PWM GENERATOR with

12-bit free-running counter and repetition

counter.

10.6.6 Input Detection Block

This block can operate in Position sensor mode, in

sensorless mode or in Speed Sensor mode. The

mode is selected via the SR bit in the MCRA reg-

ister and the TES[1:0] bits in MPAR register (refer

to Table 35 for set-up information). The block dia-

gram is shown in Figure 78 for the Position Sen-

sor/Sensorless modes (TES[1:0] = 00) and in Fig-

ure 88 for the Speed Sensor mode (TES[1:0] = 01,

10, 11).

10.6.6.1 Input Pins

The MCIA, MCIB and MCIC input pins can be

used as analog or as digital pins.

– In sensorless mode, the analog inputs are used

to measure the BEMF zero crossing and to de-

tect the end of demagnetization if required.

– In sensor mode, the analog inputs are used to

get the Hall sensor information.

– In speed sensor mode (e.g. tachogenerator), the

inputs are used as digital pins. When using an

AC tachogenerator, a small external circuit may

be needed to convert the incoming signal into a

square wave signal which can be treated by the

MTC.

Due to the presence of diodes, these pins can per-

manently support an input current of 5mA. In sen-

sorless mode, this feature enables the inputs to be

connected to each motor phase through a single

resistor.

A multiplexer, programmed by the IS[1:0] bits in

the MPHST register selects the input pins and

connects them to the control logic in either sensor-

less or tachogenerator mode. In encoder mode, it

is mandatory to connect sensor digital outputs to

the MCIA and MCIB pins.

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 77. Simplified MTC Block Diagram

MCIA

MCIB

MCIC

BEMF=0

MCO5

MCO4

MCO3

MCO2

MCO1

MCO0

PHASE

TIMER

DELAY = WEIGHT x Zn

MCCFI0

MCCREF

NMCES

DELAY

CAPTURE Zn

COMMUTE [C]

MEASUREMENT

WINDOW

GENERATOR CURRENT

VOLTAGE

MODE

Int/Ext

WEIGHT

(I) (V)

(V)

(I)

C(I)

DELAY MANAGER

CHANNEL

BEMF ZERO-CROSSING

DETECTOR

PWM MANAGER

[Z]

(V)

[Z] : Back EMF Zero-crossing event

Zn : Time elapsed between two consecutive Z events

[C] : Commutation event

Cn : Time delayed after Z event to generate C event

(I): Current mode

(V): Voltage mode

MTIM

VDD

MANAGER

12-bit counter

Phase U

Phase W

U, V, W

Phases

Phase U

Phase V

PWM GENERATOR

INPUT DETECTION

12-bit THREE-PHASE

MCVREF

OAP

OAN

MCPWMU

MCPWMV

MCPWMW

(V)

PCN bit

OAZ(MCCFI1)

OAON bit

CFAV bit

ADC

Encoder Unit

TACHO

or SPEED MEASURE UNIT (not represented)

Mix-424‘ ﬁﬂ

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 78. Input Stage in Sensorless or Sensor Mode (bits TES[1:0] = 00)

VREF

Inputn Sel Reg

VR[2:0]

MCIC

MCIA

MCIB

IS[1:0]

CS,H

Input Block Input Comparator Block Event Detection

ZVD bit

HDMn bit*

to ZH Generation

or or or

CPBn bit*

REO bit

CS,H

DS,H

CPBn bit*

12-bit PWM generator Signal U

Sampling frequency

V0C1 bit

Sample

CS,H

DS,H

* = Preload register, changes taken into account at next C event

MPHST Register

MPOL Register

MCRA Register

MCRB Register MPOL Register

MCRB Register

Reg

S,H

events:

Commutation

BEMF Zero-crossing

End Of Demagnetization

Emergency Stop

Notes

Updated/Shifted on R

Ratio Updated (+1 or -1)

Multiplier Overflow

+/-

urrent Mode

oltage Mode

Reg

Updated with Regn+1 on C

Branch taken after C event

Branch taken after D event

MCRC Register

MCVREF

PZ bit

MCRA Register

111

Sample

SPLG bit

MCRC Register

SR bit

MCRA Register

MCONF Register

DS[3:0] bits

1DWF[3:0]

MDFR Register

ZWF[3:0]

MZFR Register

SR bit

MCRA Register

to DH Generation

Z Event Generation

D Event Generation

fSCF

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.2 Sensorless Mode

This mode is used to detect BEMF zero crossing

and end of demagnetization events.

The analog phase multiplexer connects the non-

excited motor winding to an analog 100mV hyster-

esis comparator referred to a selectable reference

voltage.

IS[1:0] bits in MPHST register allow to select the

input which will be drive to the comparator (either

MCIA, B or C). Be careful that the comparator is

OFF until CKE and/or DAC bit are set in MCRA

The VR[2:0] bits in the MCRC register select the

reference voltage from seven internal values de-

pending on the noise level and the application volt-

age supply. The reference voltage can also be set

externally through the MCVREF pin when the

VR[2:0] bits are set.

Table 25. Threshold voltage setting

*Typical value for VDD=5V.

BEMF detections are performed during the meas-

urement window, when the excited windings are

free-wheeling through the low side switches and

diodes. At this stage the common star connection

voltage is near to ground voltage (instead of VDD/2

when the excited windings are powered) and the

complete BEMF voltage is present on the non-ex-

cited winding terminal, referred to the ground ter-

minal.

The zero crossing sampling frequency is then de-

fined, in current mode, by the measurement win-

dow generator frequency (SA[3:0] bits in the

MPRSR register) or, in voltage mode, by the PWM

generator frequency and phase U duty cycle.

During a short period after a phase commutation

(C event), the winding where the back-emf will be

read is no longer excited but needs a demagneti-

sation phase during which the BEMF cannot be

read. A demagnetization current goes through the

free-wheeling diodes and the winding voltage is

stuck at the high voltage or to the ground terminal.

For this reason an “end of demagnetization event”

D must be detected on the winding before the de-

tector can sense a BEMF zero crossing.

For the end-of-demagnetization detection, no spe-

cial PWM configuration is needed, the comparator

sensing is done at a selectable frequency (fSCF),

see Table 82.

So, the three events: C (commutation), D (demag-

netization) and Z (BEMF zero crossing) must al-

ways occur in this order in autoswitched mode

when hard commutation is selected.

The comparator output is processed by a detector

that automatically recognizes the D or Z event, de-

pending on the CPB or ZVD edge and level config-

uration bits as described in Table 30.

To avoid wrong detection of D and Z events, a

blanking window filter is implemented for spike fil-

tering. In addition, by means of an event counter,

software can filter several consecutive events up

to a programmed limit before generating the D or Z

event internally. This is shown in Figure 79 and

Figure 80.

VR2 VR1 VR0 Vref voltage threshold

111

Threshold voltage set by

external MCVREF pin

1 1 0 3.5V*

1 0 1 2.5V*

100 2V*

0 1 1 1.5V*

010 1V*

0 0 1 0.6V*

0 0 0 0.2V*

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MOTOR CONTROLLER (Cont’d)

10.6.6.3 D Event detection

In sensorless mode, the D Window Filter becomes

active after each C event. It blanks out the D event

during the time window defined by the DWF[3:0]

bits in the MDFR register (see Table 26). The reset

value is 200µs.

This Window Filter becomes active after both

hardware and software C events.

The D Event Filter becomes active after the D Win-

dow Filter. It counts the number of consecutive D

events up to a limit defined by the DEF[3:0] bits in

the MDFR register. The reset value is 1. The D bit

is set when the counter limit is reached.

Sampling is done at a selectable frequency

(fSCF ), see Table 82.

The D event filter is active only for a hardware D

event (DH). For a simulated (DS) event, it is forced

to 1.

Figure 79. D Window and Event Filter Flowchart

Note: Times are indicated for 4 MHz fPERIPH

Table 27. D Event filter Setting

No End of

Blanking Window

Event

Sampling

Limit=1?

Reset counter

Increment counter

Set the D bit

Counter=Limit?

Yes

WINDOW

FILTER

EVENT

FILTER

Yes

DWF3 DWF2 DWF1 DWF0

C to D window fil-

ter in Sensorless

Mode (SR=0)

SR=1

0000 5 µs

No Window Filter after C event

0001 10 µs

0010 15 µs

0011 20 µs

0100 25 µs

0101 30 µs

0110 35 µs

0111 40 µs

1000 60 µs

1001 80 µs

1010 100 µs

1011 120 µs

1100 140 µs

1101 160 µs

1110 180 µs

1111 200 µs

DEF3 DEF2 DEF1 DEF0 D event Limit SR=1

0000 1

No D Event Filter

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

End 0! Blanking E]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.4 Z Event Detection

In sensorless mode, the Z window filter becomes

active after each D event. It blanks out the Z event

during the time window defined by the ZWF[3:0]

bits in the MZFR register (see Table 28). The reset

value is 200µs. This Window Filter becomes active

after both hardware and software D events.

The Z Event Filter becomes active after the Z Win-

dow Filter. It counts the number of consecutive Z

events up to a limit defined by the ZEF[3:0] bits in

the MZFR register. The reset value is 1. The Z bit

is set when the counter limit is reached.

Sampling is done at a selectable frequency

(fSCF), see Table 82.

The Z event filter is active only for a hardware Z

event (ZH). For a simulated (ZS) event, it is forced

to 1. Z event filter is also active in sensor mode.

Figure 80. Z Window and Event Filter Flowchart

Table 28. Z Window filter Setting

Note: Times are indicated for 4 MHz fPERIPH

Table 29. Z Event filter Setting

No End of

Blanking

Event

Sampling

Limit=1?

Reset counter

Increment counter

Set the Z bit

Counter=Limit?

Yes

WINDOW

FILTER

EVENT

FILTER

Yes

Window

ZWF3 ZWF2 ZWF1 ZWF0

D to Z window fil-

ter in Sensorless

Mode (SR=0)

SR=1

0000 5 µs

Win-

dow

Filter

after

event

0001 10 µs

0010 15 µs

0011 20 µs

0100 25 µs

0101 30 µs

0110 35 µs

0111 40 µs

1000 60 µs

1001 80 µs

1010 100 µs

1011 120 µs

1100 140 µs

1101 160 µs

1110 180 µs

1111 200 µs

ZEF3 ZEF2 ZEF1 ZEF0 Z event Limit

0000 1

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

e9 e» e» jﬁé—‘i ea 6» e9 69% 3 e» e9 e» m A e» e» e» m 693 3

ST7MC1xx/ST7MC2xx

152/309

MOTOR CONTROLLER (Cont’d)

Table 30 shows the event control selected by the

ZVD and CPB bits. In most cases, the D and Z

events have opposite edge polarity, so the ZVD bit

is usually 0.

Table 30. ZVD and CPB Edge Selection Bits

Legend:

DWF= D window filter

DEF= D event filter

ZWF = Z window filter

ZEF = Z event filter

Refer also to Table 34 on page 162.

ZVD bit CPB bit Event generation vs input data sampled

Note: The ZVD bit is located in the MPOL register, the CPB bit is in the MCRB register.

DWF ZWF ZEF

DEF

ZWF DWF ZEF

DEF

ZWFDWF

DEF

ZEF

ZWFDWF

DEF

ZEF

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MOTOR CONTROLLER (Cont’d)

10.6.6.5 Demagnetization (D) Event

At the end of the demagnetization phase, current

no longer goes through the free-wheeling diodes.

The voltage on the non-excited winding terminal

goes from one of the power rail voltages to the

common star connection voltage plus the BEMF

voltage. In some cases (if the BEMF voltage is

positive and the free-wheeling diodes are at

ground for example) this end of demagnetization

can be seen as a voltage edge on the selected

MCIx input and it is called a hardware demagneti-

zation event DH. See Table 30.

The D event filter can be used to select the

number of consecutive D events needed to gener-

ate the DH event.

If enabled by the HDM bit in the MCRB register,

the current value of the MTIM timer is captured in

to be able to simulate the demagnetization phase

for the next steps.

When enabled by the SDM bit in the MCRB regis-

ter, demagnetization can also be simulated by

comparing the MTIM timer with the MDREG regis-

ter. This kind of demagnetization is called simulat-

ed demagnetization DS.

If the HDM and SDM bits are both set, the first

event that occurs, triggers a demagnetization

event. For this to work correctly, a DS event must

not precede a DH event because the latter could

be detected as a Z event.

Simulated demagnetization can also be always

used if the HDM bit is reset and the SDM bit is set.

This mode works as a programmable masking

time between the CH and Z events. To drive the

motor securely, the masking time must be always

greater than the real demagnetization time in order

to avoid a spurious Z event.

When an event occurs, (either DH or DS) the DI bit

in the MISR register is set and an interrupt request

is generated if the DIM bit of register MIMR is set.

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MDREG reg-

ister by DH and DS events, the MDREG register

should be manipulated with special care.

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation ( See “Built-in Checks and

Controls for simulated events” on page 175.), the

value written in the MDREG register in soft demag-

netisation mode (SDM=1) is checked by hardware

after the C event. If this value is less than or equal

to the MTIM counter value at this moment, the

Software demagnetisation event is generated im-

mediately and the MTIM current value overwrites

the value in the MDREG register to be able to re-

use the right demagnetisation time for another

simulated event generation.

Figure 81. D Event Generation Mechanism

MTIM [8-bit Up Counter] §

MDREG [Dn]§

Compare

HDM bit

D = DH & HDM bit + DS & SDM bit

SDM bit

F(x)

§ Register updated on R event

SDM* bit

HDMn bit*

CPBn bit*

DS,H

Sample

To Z event detection

* = Preload register, changes taken into account at next C event

To interrupt generator

MCRB Register

SPLG bit

MCRC

SR bit

MCRA Register

MDFR Register

DEF[3:0]

DWF[3:0]

MDFR Register

DWF[3:0]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Table 31. Demagnetisation (D) Event Generation (example for ZVD=0)

HDM

bit Meaning CPB bit = 1 CPB bit = 0

Simulated Mode

(SDM bit =1 and

HDM bit = 0)

D = DS = Output Compare [MDREG, MTIM registers]

Hardware/Simulat-

ed Mode

(SDM bit = 1 and

HDM bit = 1)

D = DH + DS

(Hardware detection or Output compare true)

D = DH

(Hardware detection only)

(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)

Σ2

HV/2

Σ2

HVV

HV/2

Undershoot due to

motor parasite or first Weak / null

undershoot and

(*)

sampling BEMF positive

Σ5

HVV

HV/2

(*)

Σ2

HV/2

Σ2

HV/2

Undershoot due to

motor parasite or first Weak / null

undershoot and

(*)

sampling BEMF positive

DHZ

Σ5

HV/2

(*)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.6 Z Event Generation (BEMF Zero

Crossing)

When both C and D events have occurred, the

PWM may be switched to another group of outputs

(depending on the OS[2:0] bits in the MCRB regis-

ter) and the real BEMF zero crossing sampling can

start (see Figure 87). After Z event, the PWM can

also be switched to another group of outputs be-

fore the next C event.

A BEMF voltage is present on the non-powered

terminal but referred to the common star connec-

tion of the motor whose voltage is equal to VDD/2.

When a winding is free-wheeling (during PWM off-

time) its terminal voltage changes to the other

power rail voltage, this means if the PWM is ap-

plied on the high side driver, free-wheeling will be

done through the low side diode and the terminal

will be 0V.

This is used to force the common star connection

to 0V in order to read the BEMF referred to the

ground terminal.

Consequently, BEMF reading (i.e. comparison

with a voltage close to 0V) can only be done when

the PWM is applied on the high side drivers. When

the BEMF signal crosses the threshold voltage

close to zero, it is called a hardware zero-crossing

event ZH. A filter can be implemented on the ZH

event detection (see Figure 83).

The Z event filter register (MZFR) is used to select

the number of consecutive Z events needed to

generate the ZH event. Alternatively, the PZ bit

can be used to enable protection as described in

Figure 83. on page 157

For this reason the MTC outputs can be split in two

groups called LOW and HIGH and the BEMF read-

ing will be done only when PWM is applied on one

of these two groups. The REO bit in the MPOL

BEMF sensing (high side group). It has to be con-

figured whatever the sampling mode.

When enabled by the HZ bit in MCRC register, the

current value of the MTIM timer is captured in reg-

ister MZREG when this event occurs in order to be

able to compute the real delay in the delay manag-

er part for hardware commutation but also to be

able to simulate zero-crossing events for other

steps.

When enabled by the SZ bit set in the MCRC reg-

ister, a zero-crossing event can also be simulated

by comparing the MTIM timer value with the

MZREG register. This kind of zero-crossing event

is called simulated zero-crossing ZS.

If both HZ and SZ bits are set in MCRC register,

the first event that occurs, triggers a zero-crossing

event.

Depending on the edge and level selection (ZVD

and CPB) bits and when PWM is applied on the

correct group, a BEMF zero crossing detection (ei-

ther ZH or ZS) sets the ZI bit in the MISR register

and generates an interrupt if the ZIM bit is set in

the MIMR register.

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MZREG reg-

ister by ZH and ZS events, the MZREG register

should be manipulated with special care.

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation, the value written in the

MZREG register in simuated zero-crossing mode

(SZ=1) is checked by hardware after the D (either

DH or DS) event. If this value is less than or equal

to the MTIM counter value at this moment, the sim-

ulated zero-crossing event is generated immedi-

ately and the MTIM current value overwrites the

value in the MZREG register. See “Built-in Checks

and Controls for simulated events” on page 175.

The Z event also triggers some timer/multiplier op-

erations, for more details see Section 10.6.7

3 I

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 82. Z Event Generation

ZVD bit

or or or

REO bit

CS,H

DS,H

CPBn bit*

Sample

MPOL Register

MCRB Register MPOL Register

PZ bit

MCRA Register

To D detection

SZ bit

Z = ZH& HZ bit+ ZS & SZ bit

ZHF(x)

MTIM [8-bit Up Counter] (MSB)§

MZREG [Zn]§

Compare

SZ bit

MCRC Register

MZFR register

ZWF[3:0]

§ Register updated on R event

* = Preload register, changes taken into account at next C event

SPLG bit

DS[3:0]

bits

HZ bit

MCRC Register

HZ bit

ZHZ

To interrupt generator

MZFR register

ZEF[3:0]

ZWF[3:0]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.7 Protection for ZH event detection

To avoid an erroneous detection of a hardware

zero-crossing event, a filter can be enabled by set-

ting the PZ bit in the MCRA register. This filter will

ensure the detection of a ZH event on an edge

transition between D event and ZH event.

Without this protection, ZH event detection is done

directly on the current sample in comparison with

the expected state at the output of the phase com-

parator. For example, if a falling edge transition

(meaning a transition from 1 to 0 at the output of

the phase comparator) is configured for ZH event

through the CPB bit in MCRB register, then, the

state 0 is expected at the comparator output and

once this state is detected, the ZH event is gener-

ated without any verification that the state at the

comparator output of the previous sample was 1.

The purpose of this protection filter is to be sure

that the state of the comparator output at the sam-

ple before was really the opposite of the current

state which is generating the ZH event. With this

filter, the ZH event generation is done on edge

transition level comparison.

This filter is not needed in sensor mode (SR=1)

and for simulated zero-crossing event (ZS) gener-

ation.

When the PZ bit is set, the Z event filter ZEF[3:0] in

the MZFR register is ignored.

Figure 83. Protection of ZH event detection

Sampling clock

Current sample Previous sample

Phase

Comparator

Falling/Rising Edge

MCRB register MPOL register

CPB* bit

Direct/Filter PZ

MCRA register

bit 1

ZVD bit

V Voltage mode

I Current mode

Rz Rising edge zero-crossing

Fz Falling edge zero-crossing

C Commutation event

Instantaneous

edge

CRz

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.8 Position Sensor Mode

In position sensor mode (SR=1 in MCRA register),

the rotor position information is given to the periph-

eral by means of logical data on the three inputs

MCIA, MCIB and MCIC (Hall sensors).

For each step one of these three inputs is selected

(IS[1:0] bits in register MPHST) in order to detect

the Z event. Be careful that the phase comparator

is OFF until CKE and /or DAC bits are set in MCRA

In sensor mode, Demagnetization and the related

features (such as the special PWM configuration,

DS or DH management, programmable filter) are

not available (see Table 32)

Table 32. Demagnetisation access

In sensor mode configuration the rotor detection

doesn’t need a particular phase configuration to

perform the measurement and a Z event can be

read from any detection window. The sampling is

done at a selectable frequency (fSCF), see Table

82. This means that Z event position sensoring is

more precise than it is in sensorless mode.

There is no minimum off time required for current

control PWM in sensor mode so the minimum off

time is set automatically to 0µs as soon as the SR

bit is set in the MCRA register and a true 100%

duty cycle can be set in the PWM compare U reg-

ister for the PWM generation in voltage mode.

In Sensor mode, the ZEF[3:0] bits in the MZFR

number of consecutive Z samples needed to gen-

erate the active event.

Procedure for reading sensor inputs in Direct

Access mode: In Direct Access mode, the sen-

sors can be read either when the clock are ena-

bled or disabled (depending on CKE it in MCRA

steps have to be performed:

1. Select Direct Access Mode (DAC bit in MCRA

2. Select the appropriate MCIx input pin by means

of the IS[1:0] bits in the MPHST register

3. Read the comparator output (HST bit in the

MREF register)

SR bit

MCRA register

Demagnetisation feature

availabilty

1NO

0YES

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.9 Sampling block

For a full digital solution, the phase comparator

output sampling frequency is the frequency of the

PWM signal applied to the switches and the sam-

pling for the Z event detection in sensorless mode

is done at the end of the off time of this PWM sig-

nal to avoid to have to re-create a virtual ground

because when the PWM signal is off, the star point

is at ground due to the free-wheeling diode. That’s

why, the sampling for Z event detection is done by

default during the OFF-state of the PWM signal

and therefore at the PWM frequency.

In current mode, this PWM signal is generated by

a combination of the output of the measurement

window generator (SA[3:0] bits), the output of the

current comparator and a minimum OFF time set

by the OT[3:0] bits for system stabilisation.

In voltage mode, this PWM signal is generated by

the 12-bit PWM generator signal in the compare U

the sampling is done at the end of the OFF time of

the PWM signal for system stabilisation. The PWM

signal is put OFF as soon as the current feedback

reaches the current input limitation. This can add

an OFF time to the one programmed with the 12-

bit Timer.

For D event detection in sensorless mode, no spe-

cific PWM configuration is needed and the sam-

pling frequency (fSCF, see Table 82) is completely

independent from the PWM signal.

In sensor mode, the D event detection is not need-

ed as the MCIA, MCIB and MCIC pins are the dig-

ital signals coming from the hall sensors so no

specific PWM configuration is needed and the

sampling for the Z detection event is done at

fSCF, completely independent from the PWM sig-

nal.

In sensorless mode, if a virtual ground is created

by the addition of an external circuit, sampling for

the Z event detection can be completely independ-

ent from the PWM signal applied to the switches.

Setting the SPLG bit in the MCRC register allows a

sampling frequency of fSCF for Z event detection

independent from the PWM signal after getting the

D (end of demagnetisation) event. This means that

the sampling order is given whatever the PWM

signal (during the ON time or the OFF time). As

soon as the SPLG bit is set in the MCRC register,

the minimum OFF time needed for the PWM signal

in current mode is set to 0µs and a true 100% duty

cycle can be set in the 12-bit PWM generator com-

pare register in voltage mode.

Specific applications can require sampling for the

Z event detection only during the ON time of the

PWM signal. This can happen when the PWM sig-

nal is applied only on the low side switches for Z

event detection. In this case, during the OFF time

of the PWM signal, the phase voltage is tied to the

application voltage V and no back-EMF signal can

be seen. During the ON time of the PWM signal,

the phase voltage can be compared to the neutral

point voltage and the Z event can be detected.

Therefore, it is possible to add a programmable

delay before sampling (which is normally done

when the PWM signal is switched ON) to perform

the sampling during the ON time of the PWM sig-

nal. This delay is set with the DS [3:0] bits in the

MCONF register.

Table 33. Delay length before sampling

Note: Times are indicated for 4 MHz fPERIPH

As soon as a delay is set in the DS[3:0] bits, the

minimum OFF time for the PWM signal is no long-

er required and it is automatically set to 0µs in cur-

rent mode in the internal sampling clock and a true

100% duty cycle can be set in the 12-bit PWM

generator compare U register if needed.

DS3 DS2 DS1 DS0 Delay added to

sample at Ton

0000

No delay added.

Sample during

Toff

0 0 0 1 2.5 µs

0 0 1 0 5 µs

0 0 1 1 7.5 µs

0 1 0 0 10 µs

0 1 0 1 12.5 µs

0 1 1 0 15 µs

0 1 1 1 17.5 µs

1 0 0 0 20 µs

1 0 0 1 22.5 µs

1 0 1 0 25 µs

1 0 1 1 27.5 µs

1 1 0 0 30 μs

1 1 0 1 32.5 μs

1 1 1 0 35 μs

1 1 1 1 37.5 μs

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Depending on the frequency and the duty cycle of

the PWM signal, the delay inserted before sam-

pling could cause it sample the signal OFF time in-

stead of the ON time. In this case an interrupt can

be generated and the sample will not be taken into

acount. When a sample occurs outside the PWM

signal ON time, the SOI bit in the MCONF register

is set and an interrupt request is generated if the

SOM bit is set in the MCONF register. This inter-

rupt is enabled only if a delay value has been set in

the DS[3:0] bits. In this case, the sampling is done

at the PWM frequency but only during the ON time

of the PWM signal. Figure 84 and Figure 85 shows

in detail the generation of the sampling order when

the delay is added.

For complete flexibility, the possibility of sampling

at fSCF high frequency during the ON time of the

PWM signal is also available when the SPLG bit is

set as if there is a delay value in the DS[3:0] bits.

This means that when the sampling is to be per-

formed, after the delay a sampling window at fSCF

frequency is opened until the next OFF time of the

PWM signal. The Sampling Out interrupt will be

generated if the delay added is longer than the

duty cycle of the PWM signal. As the SPLG bit is

set and a value has been put in the DS[3:0] bits,

no minimum off time is required for the PWM sig-

nal and it is automatically set to 0µs in current

mode. A true 100% duty cycle can be also set in

the 12-bit Timer in voltage mode. Figure 86 shows

in detail the sampling at fSCF high frequency dur-

ing ON time.

Figure 84. Adding the Delay to sample during ON time for Z detection

Figure 85. Sampling Out interrupt generation

PWM OFF

time Current

sample

DS[3:0]

New

sample

TSampling

PWM signal

DS[3:0]

PWM OFF

time Current

sample

DS[3:0]

TSampling

PWM signal

New sample during next

OFF time. Sample not taken into

account. SO interrupt generated.

SO To interrupt generator

ilHHHHHHi ‘JIH‘ -2 E]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

In conclusion, there are 4 sampling types that are

available for Z event detection in sensorless

mode.

1. Sampling at the end of the OFF time of the

PWM signal at the PWM frequency

2. Sampling, at a programmable frequency inde-

pendent of the PWM state (during ON time or

OFF time of the signal). Sampling is done at

fSCF, see Table 82.

3. Sampling during the ON time of the PWM sig-

nal by adding a delay at PWM frequency

4. Sampling, at a programmable frequency during

the ON time (addition of a programmable delay)

of the PWM signal. Sampling is done at fSCF,

see Table 82.

Note 1: The sampling type is applied only for Z

event detection after the D event has occured.

Whatever the sampling type for Z event detection,

the sampling of the signal for D event detection is

always done at the selected fSCF frequency (see

Table 82), independently of the PWM signal (ei-

ther during ON or OFF time). Table 34 explains the

different sampling types in sensorless and in sen-

sor mode.

Note 2: When the MOE bit in the MCRA register is

reset (MCOx outputs in reset state), and the SR bit

in the MCRA register is reset (sensorless mode)

and the SPLG bit in the MCRC register is reset

(sampling at PWM frequency) then, depending on

the state of the ZSV bit in the MSCR register, Z

event sampling can run or be stopped (and D

event is sampled).

Note 3: When BEMF sampling is performed at the

end of the PWM signal off-time, the inputs in OFF-

state are grounded or put in HiZ as selected by the

DISS bit in the MSCR register.

Note 4: The ZEF[3:0] event counter in the MZFR

Figure 86. Sampling during ON time at fSCF

PWM OFF

state Current

sample

fSCF

PWM signal

DS[3:0] DS[3:0]

during

ON time

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.10 Commutation Noise Filter

For D event detection and for Z event detection

(when SPLG bit is set while DS[3:0] bits are reset),

sampling is done at fSCF during the PWM ON or

OFF time (“Sampling block” on page 159). To

avoid any erroneous detection due to PWM com-

mutation noise, an hardware filter of 1µs (for fPER-

IPH = 4Mhz) when PWM is put ON and when PWM

is put OFF has been implemented. This means

that, with sampling at 1MHz (1µs), due to this filter,

1 sample are ignored directly after the commuta-

tion.

This filter is active all the time for the D event and

it is active for the Z event when the SPLG bit is set

and DS[3:0] bits are cleared (meaning that the Z

event is sampled at high frequency during the

PWM ON or OFF time).

Table 34. Sensor/sensorless mode and D & Z event selection

Note: For fSCF selection, see Table 82

bit

SPLG

bit

DS[3:0]

bits Mode

OS[2:0]

bits use

Event detection

sampling clock

Sampling

behaviour for

Z event

detection

Window and

Event Filters

Behaviour of the

output PWM

0 0 000 Sensors

not used Enabled

D: fSCF

Z: SA&OT config.

PWM frequency

At the end of

the off time of

the PWM sig-

nal

D Window Filter DWF[3:0] after C event

D Event Filter DEF[3:0] after DWF

Z Window Filter ZWF[3:0] after D event

Z Event Filter ZEF[3:0] after ZWF

See Table 30 on page 152

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

0 1 000 Sensors

not used Enabled D: fSCF

Z: fSCF

During off time

or ON time of

the PWM sig-

nal

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

Not

equal to

000

Sensors

not used Enabled

D: fSCF

Z: SA&OT config.

PWM frequency

During ON

time of the

PWM signal

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

Not

equal to

000

Sensors

not used Enabled D: fSCF

Z: fSCF

During ON

time of the

PWM signal

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

1x xxx

Position

Sensors

used

OS1 dis-

abled Z: fSCF

During OFF

time or ON

time of the

PWM signal

No Z Window Filter

Only Z Event Filter

is active in

Sensor mode

“Before Z” behaviour

and “after Z” behaviour

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 87. Functional Diagram of Z Detection after D Event

Begin

End

DS or DH

Change the side according to OS[2:0]

Switch Sampling Clock[D] -> Sampling Clock[Z]

Wait for next sampling clock edge

Yes

Filter

off

Read enabled

Z Window Filter turned on

ZWF[3:0] bits in MZFR register

Read enable

by REO

Side change on

Output PWM

ST7MC1xx/ST7MC2xx

164/309

MOTOR CONTROLLER (Cont’d)

10.6.6.11 Speed Sensor Mode

This mode is entered whenever the Tacho Edge

Selection bits in the MPAR register are not both re-

set (TES[1:0] = 01, 10 or 11). The corresponding

block diagram is shown in Figure 88.

Either Incremental Encoder or Tachogenerator-

type speed sensor can be selected with the IS[1:0]

bits in the MPHST register.

10.6.6.12 Tachogenerator Mode (IS[1:0] = 00, 01

or 10)

Any of the MCIx input pins can be used as a tacho-

generator input, with a digital signal (externally

amplified for instance); the two remaining pins can

be used as standard I/O ports.

A digital multiplexer connects the chosen MCIx in-

put to an edge detection block. Input selection is

done with the IS[1:0] bits in the MPHST register.

An edge selection block is used to select one of

three ways to trigger capture events: rising edge,

falling edge or both rising and falling edge sensi-

tive; set-up is done with the TES[1:0] bits (keeping

in mind that TES[1:0] = 00 configuration is re-

served for Position Sensor / Sensorless Modes).

Having only one edge selected eliminates any in-

coming signal dissymmetry, which may due to

pole-to-pole magnet dissymmetry or from a com-

parator threshold with low level signals.

Figure 89 presents the signals generated internal-

ly with different tacho input and TES bit settings.

Note on Hall Sensors: This configuration is also

suitable for motors using 3 hall sensors for position

detection and not driven in six-step mode (refer to

“Speed Measurement Mode” on page 180).

Note on initializing the Input Stage: As the

IS[1:0] bits in the MPHST register are preload bits

(new values taken into account at C event), the in-

itialization value of the IS[1:0] bits has to be en-

tered in Direct Access mode. This is done by set-

ting the DAC bit in the MCRA register during the

speed sensor input initialization routine.

Figure 88. Input Stage in Speed Sensor Mode (TES[1:0] bits = 01, 10, 11)

Inputn Sel

MCIC

MCIA

MCIB

Input Block Input Comparator Block Event Detection

MPHST Register

In1 Clk

Encoder

interface

Incremental

Direction

In2

Tacho§ or

Encoder

or or

EDIR bit

Clock

Tacho

Capture

TES[1:0]

MPAR Register

MCRC Register

Tacho§ or

Encoder

Tacho§ or

Free I/O

§ = According to IS[1:0] bits setting

IS[1:0]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.6.13 Encoder Mode (IS[1:0] = 11)

Figure 90 shows the signals delivered by a stand-

ard digital incremental encoder and associated in-

formation:

– Two 90° phased square signals with variable

frequency proportional to the speed; they

must be connected to MCIA and MCIB input

pins,

– Clock derived from incoming signal edges,

– Direction information determined by the rela-

tive phase shift of input signals ( + or -90°).

The Incremental Encoder Interface block aims at

extracting these signals. As input logic is both ris-

ing and falling edge sensitive (independently from

TES[1:0] bits setting), resulting clock frequency is

four times the one of the input signals, thus in-

creasing resolution for measurements.

It may be noticed that Direction bit (EDIR bit in

MCRC register) is read only and that it does’nt af-

fect counting direction of clocked timer (cf Section

). As a result, one cannot extract position informa-

tion from encoder inputs during speed reversal.

Figure 89. Tacho Capture events configured by the TES[1:0] bits

Figure 90. Incremental Encoder output signals and derived information

Tacho

input

Tacho

Capture

TES[1:0]=11

TES[1:0]=01

TES[1:0]=10

MCIA

MCIB

Encoder

inputs

Encoder

Direction

Clock

Sampling of MCIA to determine direction

(EDIR bit)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Note

If only one encoder output is available, it may be

input either on MCIA or MCIB and an encoder

clock signal will still be generated (in this case the

frequency will be 50% less than with two inputs.

The state of EDIR bit will depend on signals

present on MCIA and MCIB pins, the result will be

given by the sampling of MCIA with MCIB falling

edges.

10.6.6.14 Summary

Input Detection block set-up for the different avail-

able modes is summarized in the Table 35.

Table 35. Input Detection Block set-up

Input Detection

Block Mode Sensor Type Edge sensitivity SR

bit

TES[1:0] bits

(Tacho Edge

Selection)

IS[1:0] bits

(Input Selection)

Position Sensor Hall, Optical,... Both rising and falling edges 1 00

Sensorless N/A N/A 0 00

Speed Sensor

Incremental

Encoder

Both rising and falling edges

(imposed)

Any configuration dif-

ferent from 00:

01 10 11

Tachogenerator,

Hall, Optical...

Rising edge 01

Falling edge 10

Both rising and falling edges 11

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Note on using the 3 MCIx pins as standard

I/Os: When none of the MCIx pins are needed in

the application (for instance when driving an in-

duction motor in open loop), they can be used as

standard I/O ports, by configuring the Motor Con-

troller as follows: PCN=1, TES≠0 and IS=11. This

disables the MCIx alternate functions and switch-

es off the phase comparator. The state of the MCIx

pins is summarized in Table 36.

Table 36. MCIx pin configuration summary

*When PCN=0, TES=0 SR=0, inputs in OFF-state are put in HiZ or grounded depending on the value of

the DISS bit in the MSCR register.

Notes:

1. Analog input: Based on analog comparator and analog voltage reference. The corresponding digital

I/O is disabled and data in the DR register is not representative of data on the input.

2. Digital input: Use of standard VIL, VIH I/O level. This input can also be read via the associated I/O port.

PCN TES SR IS[1:0] MCIA MCIB MCIC

Input

Detection

Block Mode

Comments

000

00 Analog Input Hi-Z or GND Hi-Z or GND

Sensorless All MCIx pins are reserved

for the MTC peripheral

01 Hi-Z or GND Analog Input Hi-Z or GND

10 Hi-Z or GND Hi-Z or GND Analog input

11 NA NA NA NA

00 Analog Input Standard I/O Standard I/O Position

Sensor

From 1 to 3 MCIx pins reserved

depending on sensor

01 Standard I/O Analog Input Standard I/O

10 Standard I/O Standard I/O Analog Input

11 Standard I/O Standard I/O Standard I/O NA All MCIx pins are standard I/Os.

Phase comparator is OFF

≠0 x xx NA NA NA NA

00 x

00 Analog Input Standard I/O Standard I/O

Phase comparator is ON.

The IS[1:0] bits must not be modified

to avoid spurious event detection

in Motor Controller

01 Standard I/O Analog Input Standard I/O

10 Standard I/O Standard I/O Analog Input

11 Standard I/O Standard I/O Standard I/O NA

All MCIx pins are standard I/Os.

Recommended configuration:

phase comparator OFF

≠00 x

00 Digital Input Standard I/O Standard I/O Speed Sensor

Tachogenerator Phase comparator is OFF

01 Standard I/O Digital Input Standard I/O

10 Standard I/O Standard I/O Digital Input

11 Digital Input Digital Input Standard I/O Speed Sensor

Encoder

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.7 Delay Manager

Figure 91. Overview of MTIM Timer in Switched and Autoswitched Mode

This part of the MTC contains all the time-related

functions, its architecture is based on an 8-bit shift

left/shift right timer shown in Figure 91. The MTIM

timer includes:

– An auto-updated prescaler

– A capture/compare register for simulated de-

magnetization simulation (MDREG)

– Two cascaded capture and one compare regis-

ters (MZREG and MZPRV) for storing the times

between two consecutive BEMF zero crossings

(ZH events) and for zero-crossing event simula-

tion (ZS)

– An 8x8 bit multiplier for auto computing the next

commutation time

– One compare register for phase commutation

generation (MCOMP)

The MTIM timer module can work in two main

modes when driving synchronous motors in six-

steps mode.

In switched mode the user must process the step

duration and commutation time by software.

In autoswitched mode the commutation action is

performed automatically depending on the rotor

position information and register contents. This is

called the hardware commutation event CH. When

enabled by the SC bit in the MCRC register, com-

mutation can also be simulated by writing a value

directly in the MCOMP register that is compared

with the MTIM value. This is called simulated com-

mutation CS (See “Built-in Checks and Controls for

simulated events” on page 175.).

Both in switched mode and autoswitched mode , if

the SC bit in the MCRC register is set (software

commutation enabled), no comparison between

8-bit Up Counter MTIM §

MZREG [Zn]§

MDREG [Dn]§

Compare

ZHDH

CH,S

DS,H

ZH,S

Tratio

SDM* bit

clr 1

SWA bit

§ = Register updated on R event

To interrupt generator

MCRA register

MCRB register

Compare

SZ bit

MCRC register

ZH / ZS

MZPRV [Zn-1]§

Filter /D

MZFR register

ZWF[3:0]

Filter /C

MDFR register

DWF[3:0]

CH / CS

Compare

MCOMP [Cn+1]§

SC bit

MCRC register

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

the MCOMP and MTIM register is enabled before

a write access in the MCOMP register. This means

that if the SC bit is set and no write access is done

after in the MCOMP register, no CS commutation

event will occur.

In Speed Measurement mode, when using encod-

er or tachogenerator speed sensors (i.e. both

TES[1:0] bits in the MPAR register are not reset

and the input detection block is set-up to process

sensor signals), motor speed can be measured

but it is not possible drive a motor in six-step

mode, either sensored or sensorless.

Speed Measurement mode is useful for motors

supplied with 3-phase sinewave-modulated PWM

signals:

– AC induction motors,

– Permanent Magnet AC (PMAC) motors (al-

though it needs three position sensors, they

can be handled just like tachogenerator sig-

nals).

This mode uses only part of the Delay Manager’s

resources. For more details refer to “Speed Meas-

urement Mode” on page 180.

Table 37. Switched and Autoswitched modes

10.6.7.1 Switched Mode

This feature allows the motor to be run step-by-

step. This is useful when the rotor speed is still too

low to generate a BEMF. It can also run other

kinds of motor without BEMF generation such as

induction motors or switch reluctance motors. This

mode can also be used for autoswitching with all

computation for the next commutation time done

by software (hardware multiplier not used) and us-

ing the powerful interrupt set of the peripheral.

In this mode, the step time is directly written by

software in the commutation compare register

MCOMP. When the MTIM timer reaches this value

a commutation occurs (C event) and the MTIM

timer is reset.

At this time all registers with a preload function are

loaded (registers marked with (*) in Section

10.6.13). The CI bit of MISR is set and if the CIM

bit in the MIMR register is set an interrupt is gener-

ated.

The MTIM timer prescaler (Step ratio bits ST[3:0]

in the MPRSR register) is user programmable. Ac-

cess to this register is not allowed while the MTIM

timer is running (access is possible only before the

starting the timer by means of the CKE bit) but the

prescaler contents can be incremented/decre-

mented at the next commutation event by setting

the RMI (decrement) or RPI (increment) bits in the

MISR register. When this method is used, at the

next commutation event the prescaler value will be

updated but also all the MTIM timer-related regis-

ters will be shifted in the appropriate direction to

keep their value. After it has been taken into ac-

count, (at commutation) the RPI or RMI bit is reset

by hardware. See Table 38.

Only one update per step is allowed, so if both RPI

and RMI bits are set together by software, this

does not affect the MISR register: the write access

to these two bits together is not taken into account

and the previous state is kept. This means that if

either RPI or RMI bit was set before the write ac-

cess of both bits at the same time, this bit (RPI or

RMI) is kept at 1. If none of them was set before

the simultaneous write access, none of them will

be set after the write access.

In switched mode, BEMF and demagnetization de-

tection are already possible in order to pass in au-

toswitched mode as soon as possible but Z and D

events do not affect the timer contents.

In this mode, if an MTIM overflow occurs, it re-

starts counting from 0x00h and the OI overflow

flag in the MCRC register is set if the TES[1:0] bits

= 00.

Caution: In this mode, MCOMP must never be

written to 0.

Table 38. Step Update

SWA

bit Commutation Type MCOMP User

access

0 Switched mode Read/Write

1 Autoswitched mode Read/Write

Mode TES[1:0] CKE

bit

SWA

bit

Clock

State Read Ratio Increment

(Slow Down)

Ratio Decrement

(Speed-Up)

x xx 0 x Disabled

Always

possible

Write the ST[3:0] value directly in the MPRSR register

Switched 00 1 0 Enabled Set RPI bit in the MISR reg-

ister till next commutation

Set RMI bit in the MISR reg-

ister till next commutation

Autoswitched 00 1 1 Enabled

Automatically updated according to MZREG value

Speed

measure 01 10 11 1 x Enabled

ST7MC1xx/ST7MC2xx

170/309

MOTOR CONTROLLER (Cont’d)

Figure 92. Step Ratio Functional Diagram

fPERIPH

ST[3:0] Bits 4

1 / 2Ratio

1 / 2

Zn < 55h?

MTIM Timer = 100h?

-1

Tratio

R+

R-

2 MHz - 62.5 Hz

Ratio > 0?

Ratio = Ratio - 1

MZREG = MZREG x 2

MZPRV = MZPRV x 2

MDREG = MDREG x 2

Counter = Counter x 2

Begin

End

Yes

Z Capture with MTIM Timer Underflow (Zn < 55h)

Ratio < Fh?

Ratio = Ratio + 1

MZREG = MZREG / 2

MZPRV = MZPRV/2

MDREG = MDREG/2

Counter = Counter/2

Begin

End

Yes

MTIM Timer Overflow

MTIM Timer control over Tratio and register operation

Slow-down control Speed-up control

Compute MCOMP

MPRSR Register

MCOMP = MCOMP/2**

** Only in Auto-switched mode (SWA=1 in MCRA register)

ST7MC1xx/ST7MC2xx

171/309

MOTOR CONTROLLER (Cont’d)

10.6.7.2 Autoswitched Mode

In this mode, using the hardware commutation

event CH (SC bit reset in MCRC register), the

MCOMP register content is automatically comput-

ed in real-time as described below and in Figure

93.

The C (either CS or CH) event has no effect on the

contents of the MTIM timer.

When a ZH event occurs the MTIM timer value is

captured in the MZREG register, the previous cap-

tured value is shifted into the MZPRV register and

the MTIM timer is reset. See Figure 73.

When a ZS event occurs, the value written in the

MZREG register is shifted into the MZPRV register

and the MTIM timer is reset.

One of these two registers, (when the SC bit = 0 in

the MCRC register and depending on the DCB bit

in the MCRA register), is multiplied with the con-

tents of the MWGHT register and divided by 256.

The result is loaded in the MCOMP compare reg-

ister, which automatically triggers the next hard-

ware commutation (CH event).

Note: The result of the 8*8 bit multiplication, once

written in the MCOMP register is compared with

the current MTIM value to check that the MCOMP

value is not already less than the MTIM value due

to the multiplication time. If MCOMP<=MTIM, a CH

event is generated immediately and the MCOMP

value is overwritten by the MTIM value.

Table 39. Multiplier Result

After each shift operation the multiply is recomput-

ed for greater precision.

Using either the MZREG or MZPRV register de-

pends on the motor symmetry and type.

The MWGHT register gives directly the phase shift

between the motor driven voltage and the BEMF.

This parameter generally depends on the motor

and on the speed.

Setting the SC bit in the MCRC register enables

the simulated commutation event (CS) generation.

This means that a write access is possible to the

MCOMP register and the MTIM value will be com-

pared directly with the value written by software in

the MCOMP register to generate the CS event.

The comparison is enabled as soon as a write ac-

cess is done to the MCOMP register. This means

that if the SC bit is set and no write access is done

to the MCOMP register, the C event will never oc-

cur because no comparison will be done between

MCOMP and MTIM. Therefore, it is recommended

in autoswitched mode, when using software com-

mutation feature (SC bit is set) and for a normal

event sequence, the corresponding value to be

put in MCOMP has to be written during the Z inter-

rupt routine (because MTIM has just been reset),

so that there is no spurious comparison. If the SC

bit is set during a Z event interrupt, then , the result

of the 8*8 bits hardware multiplication can be over-

written by software in the MCOMP register. When

simulated commutation mode is enabled, the

event sequence is no longer respected, meaning

that the peripheral will accept consecutive commu-

tation events and not necessarily wait for a D

event after a Cs event. In this case the MCOMP

ous C event, in the C interrupt service routine for

example.

Figure 93. CH Processor Block

Note 1: An overflow of the MTIM timer generates

an RPI interrupt if the RIM bit is set.

Note 2: When simulated commutation mode is en-

abled, the D and Z event are not ignored by the

peripheral, this means that if a Z event happens,

the MTIM 8 bit internal counter will be reset.

Note 3: To generate consecutive simulated com-

mutations (CS), the successive value has to be

written in the MCOMP register only after a C event

DCB bit Commutation Delay

0 MCOMP = MWGHT x MZPRV / 256

1 MCOMP = MWGHT x MZREG / 256

MWGHT [an+1]

MZREG [Zn]§

A x B / 256

MZPRV [Zn-1]§

DCB bit

SWA bit =1 &

MCOMP [Cn+1]§

ZH/ZS

nn-1

§ = Register updated on R event

MCRA Register

SC bit =0

MCRC register

ST7MC1xx/ST7MC2xx

172/309

MOTOR CONTROLLER (Cont’d)

generation. Otherwise, the C event will never oc-

cur.

Note 4: When simulated commutation mode is en-

abled, the built-in check is active, so if the value

written in the MCOMP register is less than or equal

to MTIM, the C event is generated and the data in

the MCOMP register are overwritten by the MTIM

value.

Auto-updated Step Ratio Register:

a) In switched mode: the MTIM timer is driven by

software only and any prescaler change has to be

done by software (see page 169 for more details).

b) In autoswitched mode: an auto-updated pres-

caler always configures the MTIM timer for best

accuracy. Figure 92 shows the process of updat-

ing the Step Ratio bits:

– When the MTIM timer value reaches 100h, the

prescaler is automatically incremented in order

to slow down the MTIM timer and avoid an over-

flow. To keep consistent values, the MTIM regis-

ter and all the relevant registers are shifted right

(divided by two). The RPI bit in the MISR register

is set and an interrupt is generated (if RIM is set).

The timer restarts counting from its median value

0x80h and if the TES[1:0] bits = 00, the OI bit in

the MCRC register is set.

– When a Z-event occurs, if the MTIM timer value

is below 55h, the prescaler is automatically dec-

remented in order to speed up the MTIM timer

and keep precision better than 1.2%. The MTIM

left (multiplied by two). The RMI bit in the MISR

is set.

– If the prescaler contents reach the value 0, it can

no longer be automatically decremented, the

MTC continues working with the same prescaler

value, i.e. with a lower accuracy. No RMI in-

terrrupt can be generated.

– If the prescaler contents reach the value 15, it

can no longer be automatically incremented.

When the timer reaches the value FFh, the pres-

caler and all the relevant registers remain un-

changed and no interrupt is generated, the timer

restarts counting from 0x00h and if the TES[1:0]

bits = 00, the OI bit in the MCRC register is set at

each overflow (it has to be reset by software).

The RPI bit is no longer set. The PWM is still gen-

erated and the D and Z detection circuitry still

work, enabling the capture of the maximum timer

value.

The automatically updated registers are: MTIM,

MZREG, MZPRV, MCOMP and MDREG. Access

to these registers is summarized in Table 41.

10.6.7.3 Debug Option

In both Switched Mode and Autoswitched Mode,

setting the bit DG in MPWME register enables the

Debug Option. This option consists of outputting

the C, D and Z signals in real time on pins MCZEM

and MCDEM. This is very useful during the debug

phase of the application. Figure 94 shows the sig-

nals output on pins MCDEM and MCZEM with the

debug option.

Note 1: When the delay coefficient equals 0/256

(C event immediately after Z event), a glitch ap-

pears on MCZEM pin to be able to see the event

even in this case.

This option is also available in Speed measure-

ment mode with different signal outputs (see Fig-

ure 94):

– MCDEM toggles when a capture event is gener-

ated,

– MCZEM toggles every time a U event is gener-

ated.

These signals are only available if the TES[1:0]

bits = 10, 01 or 11.

Note 2: In sensor mode, the MCDEM output pin

toggles at each C event. The MCZEM pin outputs

the Z event.

ST7MC1xx/ST7MC2xx

173/309

MOTOR CONTROLLER (Cont’d)

Figure 94. Output on pins MCDEM and MCZEM with debug option (DG bit=1)

CCC

Z D ZDZ

MCDEM

MCZEM

U events

MCDEM

MCZEM

CCCCCC CCCC

Debug outputs in Speed Measurement mode (TES[1:0] bits equal to 01, 10 or 11).

Debug outputs in Sensorless mode

CCC

CZZ Z

MCDEM

MCZEM

Debug outputs in Sensor mode

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Note on using the auto-updated MTIM timer:

The auto-updated MTIM timer works accurately

within its operating range but some care has to be

taken when processing timer-dependent data such

as the step duration for regulation or demagnetiza-

tion.

For example if an overflow occurs when calculat-

ing a simulated end of demagnetization

(MCOMP+demagnetisation_time>FFh), the value

that is stored in MDREG will be:

80h+(MCOMP+demagnetization_time-FFh)/2.

Note on commutation interrupts: It is good prac-

tice to modify the configuration for the next step as

soon as possible, i.e within the commutation inter-

rupt routine.

All registers that need to be changed at each step

have a preload register that enables the modifica-

tions for a complete new configuration to be per-

formed at the same time (at C event in normal

mode or when writing the MPHST register in direct

access mode).

These configuration bits are:

CPB, HDM, SDM and OS2 in the MCRB register

and IS[1:0], OO[5:0] in the MPHST register.

Note on initializing the MTC: As shown in Table 41

all the MTIM timer registers are in read-write mode

until the MTC clock is enabled (with the CKE bit).

This allows the timer, prescaler and compare reg-

isters to be properly initialized for start-up.

In sensorless mode, the motor has to be started in

switched mode until a BEMF voltage is present on

the inputs. This means the prescaler ST[3:0] bits

and MCOMP register have to be modified by soft-

ware. When running the ST[3:0] bits can only be

incremented / decremented, so the initial value is

very important.

When starting directly in autoswitched mode (in

sensor mode for example), write an appropriate

value in the MZREG and MZPRV register to per-

form a step calculation as soon as the clock is en-

abled.

ST7MC1xx/ST7MC2xx

175/309

MOTOR CONTROLLER (Cont’d)

10.6.7.4 Built-in Checks and Controls for

simulated events

As described in Figure 91. on page 168, MZREG,

MDREG and MCOMP registers are capture/com-

pare registers. The Compare registers are write

accessible and can be used to generate simulated

events. The value of the MTIM timer is compared

with the value written in the registers and when the

MTIM value reaches the corresponding register

value, the simulated event is generated. Simulated

event generation is enabled when the correspond-

ing bits are set:

– In the MCRB register for simulated demagneti-

sation

– SDM for simulated demagnetisation

– In the MCRC register for simulated zero-crossing

and commutation.

– SC for simulated commutation

– SZ for simulated zero-crossing event.

To avoid a system stop, special attention is need-

ed when writing in the register to generate the cor-

responding simulated event. The value written in

the register has to be greater than the current val-

ue of the MTIM timer when writing in the registers.

If the value written in the registers (MDREG,

MZREG or MCOMP) is already less than the cur-

rent value of MTIM, the simulated event will never

be generated and the system will be stopped.

For this reason, built-in checks and controls have

been implemented in the MTIM timer.

If the value written in one of those registers in sim-

ulated event generation mode is less than or equal

to the current value of the timer when it is com-

pared, the simulated event is generated immedi-

ately and the value of the MTIM timer at the time

the simulated event occurs overwrites the value in

the registers. Like that the value in the register re-

ally corresponds to the simulated event generation

and can be re-used to generate the next simulated

event.

So, the value written in the registers able to gener-

ate simulated events is checked by hardware and

compare to the current MTIM value to verify that it

is greater.

Figure 95. Simulated demagnetisation / zero-crossing event generation (SC=0)

During C interrupt

Simulated or Hardware D/Z events

Value written in MDREG/MZREG if

simulated event generation

ZSZS

After C interrupt

MDREG value checked

if MDREG<=MTIM

Immediate DS generation

After D interrupt

MZREG value checked

if MZREG<=MTIM

Immediate ZS generation

ZS Simulated zero-crossing

DS Simulated demagnetisation

ZH Hardware zero-crossing

CH Hardware commutation

MTIM Timer Value

ST7MC1xx/ST7MC2xx

176/309

MOTOR CONTROLLER (Cont’d)

When using hardware commutation CH, the se-

quence of events needed is CH then D and finally

Z events and the value written in the registers are

checked at different times.

If SDM bit is set, meaning simulated demagnetisa-

tion, a value must be written in the MDREG regis-

ter to generate the simulated demagnetisation.

This value must be written after the C (either Cs or

CH) event preceding the simulated demagnetisa-

tion.

If SZ bit is set, meaning simulated zero-crossing

event, a value must be written in the MZREG reg-

ister to generate the simulated zero-crossing. This

value must be written after the D event (DH or DS)

preceding the simulated zero-crossing.

When using simulated commutation (CS), the re-

sult of the 8*8 hardware multiplication of the delay

manager is not taken in account and must be over-

written if the SC bit has been set in a Z event inter-

rupt and the sequence of events is broken mean-

ing that several consecutive simulated commuta-

tions can be implemented.

As soon as the SC bit is set in the MCRC register,

the system won’t necessarily expect a D event af-

ter a C event. This can be used for an application

in sensor mode with only one Hall Effect sensor for

example.

Be careful that the D and Z events are not ignored

by the peripheral, this means that for example if a

Z event occurs, the MTIM timer is reset. In Simu-

lated Commutation mode, the sequence D -> Z is

expected, and this order must be repected.

As the sequence of events may not be the same

when using simulated commutation, as soon as

the SC bit is set, the capture/compare feature and

protection on MCOMP register is reestablished

only after a write to the MCOMP register. This

means that as soon as the SC bit is set, if no write

access is done to the MCOMP register, no com-

mutation event will be generated, whatever the

value of MCOMP compared to MTIM at the time

SC is set. This does not depend on the running

mode: switched or autoswitched mode (SWA bit).

If software commutation event is used with a nor-

mal sequence of events C-->D-->Z, it is recom-

mended to write the MCOMP register during the Z

interrupt routine to avoid any spurious comparison

as several consecutive Cs events can be generat-

ed.

Note that two different simulated events can be

used in the same step (like DS followed by ZS).

Note also that for more precision, it is recommend-

ed to use the value captured from the preceding

hardware event to compute the value used to gen-

erate simulated events.

Figure 95, Figure 96 and Figure 97 shows details

of simulated event generation.

ST7MC1xx/ST7MC2xx

177/309

MOTOR CONTROLLER (Cont’d)

Figure 96. Simulated commutation event generation with only 1 Hall effect sensor (SC bit =1)

Note: If the SC bit is set during Z event interrupt,

then the 8*8 bit hardware multiplication result must

be overwritten in the MCOMP register. Otherwise,

when the SC bit is set, the result of the multiplica-

tion is not taken into account after a Z event.

Figure 97. Simulated commutation and Z event

C interrupt

SC set in MCRC

After C interrupt

MCOMP is written for Cs event

if MCOMP<=MTIM

Immediate CS generation

C interrupt

SC reset in MCRB

Next C event = CH with 8*8 bit multiplication

Z zero-crossing event

D Demagnetisation event

CH Hardware commutation

CS Simulated commutation

MTIM Timer Value

ZZZ

SC bit is reset

Z zero-crossing event

D Demagnetisation event

CH Hardware commutation

CS Simulated commutation

MCOMP

the result of the

hardware multiplication is put

in MCOMP-->CH and compared

SC bit is set during Z IT

the hardware multiplication is taken

into account but the value in MCOMP

can be overwritten

SC bit is already set when Z IT

occurs. The hardware multipli-

-cation is not taken into account

A value has to be written

in the MCOMP register

MTIM Timer Value

with MTIM once written

ST7MC1xx/ST7MC2xx

178/309

MOTOR CONTROLLER (Cont’d)

The Figure 98 gives the step ratio register value

(left axis) and the number of BEMF sampling dur-

ing one electrical step with the corresponding ac-

curacy on the measure (right axis) as a function of

the mechanical frequency.

For a given prescaler value (step ratio register) the

mechanical frequency can vary between two fixed

values shown on the graph as the segment ends.

In autoswitched mode, this register is automatical-

ly incremented/decremented when the step fre-

quency goes out of this segment.

At fMTC=4MHz, the range covered by the Step Ra-

tio mechanism goes from 2.39 to 235000 (pole

pair x rpm) with a minimum accuracy of 1.2% on

the step period.

To read the number of samples for Zn within one

step (right Y axis), select the mechanical frequen-

cy on the X axis and the sampling frequency curve

used for BEMF detection (PWM frequency or

measurement window frequency). For example,

for N.Frpm = 15,000 and a sampling frequency of

15kHz, there are approximately 10 samples in one

step and there is a 10% error rate on the measure-

ment.

Figure 98. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate

Step Ratio (Decimal)

N.Frpm

2.39

4.79

7.18

9.57

14.4

19.1

28.7

38.3

57.4

76.6

115

153

230

306

460

614

920

1230

1840

2450

3680

4900

7350

9800

14700

19600

29400

39200

58800

78400

118000

157000

235000

avg Zn ~ 7Fh ± 0.6%

100%

BEMF

samples ΔZn/Zn

10%

50%

200 Hz

15 kHz

avg Zn ~ FFh ± 0.4%

avg Zn ~ 7Fh ± 0.6%

avg Zn ~ FFh ± 0.4%

avg Zn ~ 55h ± 1.2%

3.Fn

Fn+1 = 2.Fn

3.Fn+1 = 6.Fn

Fstep = 6.N.Frpm = N.F / 10 ⇔ N.F = 10.Fstep

N: Pole pair number

Fstep: Electrical step frequency

ST[3:0]

avg Zn ~ 55h ± 1.2%

ST7MC1xx/ST7MC2xx

179/309

MOTOR CONTROLLER (Cont’d)

Table 40. Step Frequency/Period Range (4MHz)

Table 41. Modes of Accessing MTIM Timer-Related Registers

Step Ratio Bits

ST[3:0] in MPRSR

Maximum

Step Frequency

Minimum

Step Frequency

Minimum

Step Period

Maximum

Step Period

0000 23.5 kHz 7.85 kHz 42.5 μs 127.5 μs

0001 11.7 kHz 3.93 kHz 85 μs 255 μs

0010 5.88 kHz 1.96 kHz 170 μs 510 μs

0011 2.94 kHz 980 Hz 340 μs1.02ms

0100 1.47 kHz 490 Hz 680 μs2.04ms

0101 735 Hz 245 Hz 1.36 ms 4.08 ms

0110 367 Hz 123 Hz 2.72 ms 8.16 ms

0111 183 Hz 61.3 Hz 5.44 ms 16.32 ms

1000 91.9 Hz 30.7 Hz 10.9 ms 32.6 ms

1001 45.9 Hz 15.4 Hz 21.8 ms 65.2 ms

1010 22.9 Hz 7.66 Hz 43.6 ms 130 ms

1011 11.4 Hz 3.83 Hz 87 ms 261 ms

1100 5.74 Hz 1.92 Hz 174 ms 522 ms

1101 2.87 Hz 0.958 Hz 349 ms 1.04 s

1110 1.43 Hz 0.479 Hz 697 ms 2.08 s

1111 0.718 Hz 0.240 Hz 1.40 s 4.17 s

State of MCRA / MCRB / MPAR Register Bits Access to MTIM Timer Related Registers

RST bit TES[1:0] SWA bit CKE bit Mode Read Only

Access Read / Write Access

0 xx x 0 Configuration Mode MTIM, MTIML, MZPRV, MZREG,

MCOMP, MDREG, ST[3:0]

0 00 0 1 Switched Mode MTIM, ST[3:0]

MCOMP, MDREG, MZREG, MZPRV

RMI bit of MISR:

0: No action

1: Decrement ST[3:0]

RPI bit of MISR:

0: No action

1: Increment ST[3:0]

0 00 1 1 Autoswitched Mode MTIM, ST[3:0]

MDREG, MCOMP, MZREG, MZPRV,

RMI, RPI bit of MISR:

Set by hardware, (increment ST[3:0])

Cleared by software

x 1 Speed Sensor Mode MTIM, MTIML,

ST[3:0]

MDREG,MZREG, MZPRV,

RMI, RPI bit of MISR, :

Set by hardware, (increment or decre-

ment ST[3:0]), cleared by software.

4M ﬁﬁ

ST7MC1xx/ST7MC2xx

180/309

MOTOR CONTROLLER (Cont’d)

10.6.7.5 Speed Measurement Mode

Motor speed can be measured using two methods

depending on sensor type: period measurement or

pulse counting. Typical sensor handling is de-

scribed here.

Incremental encoders allows accurate speed

measurement by providing a large number of puls-

es per revolution (ppr) with ppr rates up to several

thousands; the higher the ppr rate, the higher the

resolution. The proposed method consists of

counting the number of clock cycles issued by the

Incremental Encoder Interface (Encoder Clock)

during a fixed time window (refer to Figure 100).

The tachogenerator has a much lower ppr rate

than the encoder (typically factor 10). In this con-

text, it is more meaningful to measure the period

between Tacho Captures (i.e. relevant transitions

of the incoming signals). Accuracy is imposed by

the reference clock, i.e. the CPU clock (refer to

Figure 99).

Figure 99. Tachogenerator period acquisition using MTIM timer

Figure 100. Encoder Clock frequency measure using MTIM timer

C C C C C C

Comparator

Output

Tacho

Capture

Compare

Value

MTIM Counter

Value

Interrupts

Decreasing Speed

CTo interrupt generatorTo interrupt generator

(Capture Event) (Speed Error Event)

Encoder

Clock

Capture

(triggered by software

MTIM Counter

Value

C C C C C C C

Interrupts

Decreasing Speed

CTo interrupt generator

(Capture Event)

or Real-time Clock)

ST7MC1xx/ST7MC2xx

181/309

MOTOR CONTROLLER (Cont’d)

Hall sensors (or equivalent sensors providing posi-

tion information) are widely used for motor control.

There are two cases to be considered:

– BLDC motor or six-step synchronous motor

drive; “Sensor Mode” is recommended in this

case, as most tasks are performed by hardware

in the Delay Manager

– BLAC, asynchronous or motors supplied with 3-

phase sinewave-modulated PWM signals in gen-

eral; in this case “Speed Sensor Mode” allows

high accuracy speed measurement (the Sensor

Mode of the Delay Manager being unsuitable for

sinewave generation). Position information is

handled by software to lock the statoric field to

the rotoric one for driving synchronous motors.

Hall sensors are usually arranged in a 120° config-

uration. In that case they provide 3 ppr with both

rising and falling edge triggering; the tachogenera-

tor measurement method can therefore be ap-

plied. The main difference lies in the fact that one

must use the position information they provide.

This can be done using the three MCIx pins and

the analog multiplexer to know which of the 3 sen-

sors toggled; an interrupt is generated just after

the expected transition (refer to Figure 101).

As described in Figure 102, the MTIM Timer is re-

configured depending on the selected sensor. This

means that most of Delay Manager registers are

used for a different purpose, with modified func-

tionalities.

For greater precision, the MTIM Up-counter is ex-

tended to 16 bits using MTIM and an additional

MTIML register. On a capture event, the current

counter value is captured and the counter

[MTIM:MTIML] is cleared. The counting direction

is not affected by the EDIR bit when using an en-

coder sensor.

A 16-bit capture register is used to store the cap-

tured value of the extended MTIM counter: the

speed result will be either a period in clock cycles

or a number of encoder pulses. This 16-bit register

is mapped in the MZREG and MZPRV register ad-

dresses. To ensure that the read value is not cor-

rupted between the high and low byte accesses, a

read access to the MSB of this register (MZREG)

locks the LSB (ie MZPRV content is locked) until it

is read and any other capture event in between

these two accesses is discarded.

A compare unit allows a maximum value to be en-

tered for the tacho periods. If the 16-bit counter

[MTIM:MTIML] exceeds this value, a Speed Error

interrupt is generated. This may be used to warn

the user that the tachogenerator signal is lost

(wires disconnected, motor stalled,...). As 8-bit ac-

curacy is sufficient for this purpose, only the MS-

Byte of the counter (i.e. MTIM) is compared to 8-bit

compare register, mapped in the MDREG register

location. The LSByte is nevertheless compared

with a fixed FFh value. Available values for com-

parison are therefore FFFFh, FEFFh, FDFFh, ...,

01FFh, 00FFh.

Note: This functionality is not useful when using

an encoder. With an encoder, user must monitor

the captured values by software during the period-

ic capture interrupts: for instance, when driving an

AC motor, if the values are too low compared to

the stator frequency, a software interrupt may be

triggered.

Figure 101. Hall sensor period acquisition using MTIM timer

1 mechanical cycle

MCIA: Hall Sensor 1

MCIB: Hall Sensor 2

MCIC: Hall Sensor 3

Tacho Capture

Period measurements

C C C CC CCC C CC C C

Interrupts

1-2 3-12-3 3-11-2 2-3

ST7MC1xx/ST7MC2xx

182/309

MOTOR CONTROLLER (Cont’d)

Figure 102. Overview of MTIM Timer in Speed Measurement Mode

§ = Register updated on R event

To interrupt generator

Compare

Clock

MSbits

clr C

16-bit Up Counter

MTIM§MTIML§

16-bit Capture Register

MZREG MZPRV

LSbits

MDREG

(16MHz)

ST[3:0] Bits 41 / 2Ratio

MZREG < 55h?

MTIM Register = 100h?

-1 Tratio

RPI

RMI

MPRSR Register

IS[1:0] bits

Encoder

Clock

TES[1:0] bits

MPAR* and MPHST*

IS[1:0] TES[1:0]

Registers: MSCR* MPHST* MPAR*

ECM

Tacho Capture

MTIM Read access

RTC interrupt

(Capture Event)

(Speed Error Event)

Compare

FFh (Fixed)

16 MHz - 500 Hz

RPI To interrupt generator

RMI To interrupt generator

(Ratio Increment Event)

(Ratio Decrement Event)

Bits:

Registers

Notes:

* = Register set-up described in

Speed Sensor Mode Section

(4MHz)

fMTC fPERIPH

‘ OW»

ST7MC1xx/ST7MC2xx

183/309

MOTOR CONTROLLER (Cont’d)

A logic block manages capture operations de-

pending on the sensor type. A capture is initiated

on an active edge (“Tacho capture” event) when

using a tachogenerator.

If an encoder is used, the capture is triggered on

two events depending on the Encoder Capture

Mode bit (ECM) in the MZFR register:

– Reading the MSB of the counter in manual

mode (ECM = 1)

– Interrupt from the Real-time Clock in automat-

ic mode (ECM = 0)

The clock source of the counter is selected de-

pending on sensor type:

– Motor Control Peripheral clock (16 MHz) with

tachogenerator or Hall sensors

– Encoder Clock

In order to optimize the accuracy of the measure-

ment for a wide speed range, the auto-updated pr-

escaler functionality is used with slight modifica-

tions compared to Sensor/Sensorless Modes (re-

fer to Figure 103 and Table 38).

– When the [MTIM:MTIML] timer value reaches

FFFFh, the prescaler is automatically increment-

ed in order to slow down the counter and avoid

an overflow. To keep consistent values, the

MTIM and MTIML registers are shifted right (di-

vided by two). The RPI bit in the MISR register is

set and an interrupt is generated (if RIM is set).

– When a capture event occurs, if the

[MTIM:MTIML] timer value is below 5500h, the

prescaler is automatically decremented in order

to speed up the counter and keep precision bet-

ter than 0.005% (1/5500h). The MTIM and

MTIML registers are shifted left (multiplied by

two). The RMI bit in the MISR register is set and

an interrupt is generated if RIM is set.

– If the prescaler contents reach the value 0, it can

no longer be automatically decremented, the

[MTIM:MTIML] timer continues working with the

same prescaler value, i.e. with a lower accuracy.

No RMI interrrupt can be generated.

– If the prescaler contents reach the value 15, it

can no longer be automatically incremented.

When the timer reaches the value FFFFh, the pr-

escaler and all the relevant registers remain un-

changed and no interrupt is generated, the timer

clock is disabled, and its contents stay at FFFFh.

The capture logic block still works, enabling the

capture of the maximum timer value.

The only automatically updated registers for the

Speed Sensor Mode are MTIM and MTIML. Ac-

cess to Delay manager registers in Speed Sensor

Mode is summarised in Table 41.

Figure 103. Auto-updated prescaler functional diagram

Ratio > 0?

Ratio = Ratio - 1

Counter = 0

Begin

End

Yes

Capture with [MTIM:MTIML] Timer < 5500h

Ratio < Fh?

Ratio = Ratio + 1

Counter = Counter/2

Begin

End

Yes

[MTIM:MTIML] Timer Overflow

Slow-down control Speed-up control

(MTIM = MTIML = FFh) (MZREG < 55h)

[3\D\

ST7MC1xx/ST7MC2xx

184/309

MOTOR CONTROLLER (Cont’d)

Three kinds of interrupt can be generated in

Speed Sensor Mode, as summarized in Figure

104:

– C interrupt, when a capture event occurs; this in-

terrupt shares resources (Mask bit and Flag) with

the Commutation event in Switched/Au-

toswitched Mode, as these modes are mutually

exclusive.

– RPI/RMI interrupts occur when the ST[3:0] bits of

the MPSR register are changed, either automat-

ically or by hardware.

– S interrupt occurs when a Speed Error happens

(i.e. a successful comparison between

[MTIM:MTIML] and [MDREG:FF]). This interrupt

has the same channel as the Emergency Stop in-

terrupt (MCES), as it also warns the user about

abnormal system operation. The respective Flag

bits have to be tested in the interrupt service rou-

tine to differentiate Speed Errors from Emergen-

cy Stop events.

These interrupts may be masked individually.

Note on Delay Manager Initialization in Speed

Measurement Mode: In order to set-up the

[MTIM:MTIML] counter properly before any speed

measurement, the following procedure must be

applied:

– The peripheral clock must be disabled (resetting

the CKE bit in the MCRA register) to allow write

access to ST[3:0], MTIM and MTIML (refer to Ta-

ble 41),

– MTIM, MTIML must be reset and appropriate val-

ues must be written in the ST[3:0] prescaler

adapt to the frequency of the signal being meas-

ured and to allow speed measurement with suffi-

cient resolution.

Note on MTIML: The Least Significant Byte of the

counter (MTIML) is not used when working in Po-

sition Sensor or Sensorless Modes.

Debug option: a signal reflecting the capture

events may be output on a standard I/O port for de-

bugging purposes. Refer to section10.6.7.3 on

page 172 for more details.

Figure 104. Prescaler auto-change example

CC C C C

RPI RMI

CAPTURE

FFFFh

FAFFh

8000h

5500h

EVENTS

USUAL

WORKING

RANGE

RPI

Events:

Capture

Speed Error

Ratio Increment

RMI

Ratio Decrement

Notes:

[MTIM:MTIML]

[MTIM:MTIML] Input Clock:

/ 2

(ST[3:0] = n)

(ST[3:0] = n+1)

ST7MC1xx/ST7MC2xx

185/309

MOTOR CONTROLLER (Cont’d)

10.6.7.6 Summary

The use of the Delay manager registers for the

various available modes is summarized in Table

42.

Table 42. MTIM Timer-related Registers

10.6.8 PWM Manager

The PWM manager controls the motor via the six

output channels in voltage mode or current mode

depending on the V0C1 bit in the MCRA register.

A block diagram of this part is given in Figure 106.

10.6.8.1 Voltage Mode

In Voltage mode (V0C1 bit = ”0”), the PWM signal

which is applied to the switches is generated by

the 12-bit PWM Generator compare U.

Its duty cycle is programmed by software (refer to

the PWM Generator section) as required by the

application (speed regulation for example).

The current comparator is used for safety purpos-

es as a current limitation. For this feature, the de-

tected current must be present on the MCCFI pin

and the current limitation must be present on pin

MCCREF. This current limitation is fixed by a volt-

age reference depending on the maximum current

acceptable for the motor. This current limitation is

generated with the VDD voltage by means of an

external resistor divider but can also be adjusted

with an external reference voltage (≤ 5 V). The ex-

ternal components are adjusted by the user de-

pending on the application needs. In Voltage

mode, it is mandatory to set a current limitation. As

this limitation is set for safety purposes, an inter-

rupt can be generated when the motor current

feedback reaches the current limitation in voltage

mode. This is the current limitation interrupt and it

is enabled by setting the corresponding CLM bit in

the MIMR register. This is useful in voltage mode

for security purposes.

The PWM signal is directed to the channel manag-

er that connects it to the programmed outputs (see

Figure 106).

Name Reset Value Switched / Auto Switched Mode Speed Measurement Mode

MTIM 00h Timer Value 16-bit Timer MSB Value

MTIML 00h N/A 16-bit Timer LSB Value

MZREG 00h Capture/compare Zn Capture of 16-bit Timer MSB

MZPRV 00h Capture Zn-1 Capture of 16-bit Timer LSB

MCOMP 00h Compare Cn+1 N/A

MDREG 00h Demagnetization Dn Compare for Speed Error

interrupt generation

ST7MC1xx/ST7MC2xx

186/309

MOTOR CONTROLLER (Cont’d)

10.6.8.2 Over Current Handling in Voltage

mode

When the current limitation interrupt is enabled by

setting the CLIM bit in the MIMR register (available

only in Voltage mode), the OCV bit in MCRB reg-

ister will determine the effect of this interrupt on

the MCOx outputs as shown in Table 43.

Table 43. OCV bit effect

For safety purposes, it can be necessary to put all

MCOx outputs in reset state (high impedance,

high state or low state depending on the setting

made by the option byte) on a current limitation in-

terrupt. This is the purpose of the OCV bit. When a

current limitation interrupt occurs, if the OCV bit is

reset, the effect on the MCOx outputs is only to put

the PWM signal OFF on the concerned outputs. If

the OCV bit is set, when the current limitation inter-

rupt occurs, all the MCOx outputs are put in reset

state.

Note 1: Only this functionality (CLIM = CLI = OCV

= 1) is valid when the 3 PWM channels are ena-

bled (PCN bit =1 in the MDTG register). It can also

be used as an over-current protection for three-

phase PWM application (only if voltage mode is

selected)

10.6.8.3 Current Mode

In current mode, the PWM output signal is gener-

ated by a combination of the output of the meas-

urement window generator (see Figure 107) and

the output of the current comparator, and is direct-

ed to the output channel manager as well (Figure

108).

The current reference is provided to the compara-

tor by Phase U, V or W of the PWM Generator (up

to 12-bit accuracy) the signal from the three com-

pare registers U, V or W can be output by setting

the PWMU, PWMV or PWMW bits in the MPWME

ternal RC filter on pin MCCREF.

The detected current input must be present on the

MCCFI pin.

10.6.8.4 Current Feedback Comparator

Two programmable filters are implemented:

– A blanking window ( Current Window Filter) after

PWM has been switched ON to avoid spurious

PWM OFF states caused by parasitic noise

– An event counter (Current Feedback Filter) to

prevent PWM being turned OFF when the first

comparator edge is detected.

Figure 105. Current Window and Feedback

Filters

CLIM bit CLI bit OCV bit Output effect Interrupt

00x

Normal running

mode No

01x

PWM is put OFF

on Current loop

effect

10x

Normal running

mode No

110

PWM is put OFF

on Current loop

effect

Yes

111

All MCOx outputs

are put in reset

state (MOE re-

set)1)

Yes

PWM on

No End of

Blanking Window

Current >

Limit

Limit=1?

Reset counter

Increment counter

Set the CL bit

Counter=

Yes

WINDOW

FILTER

FEEDBACK

FILTER

Limit?

CURRENT

Yes

ST7MC1xx/ST7MC2xx

187/309

MOTOR CONTROLLER (Cont’d)

Table 44. Current Window filter Setting

Note: Times are indicated for 4 MHz fPERIPH

The Current Window filter is activated each time

the PWM is turned ON. It blanks the output of the

current comparator during the time set by the

CFW[2:0] bits in the MCFR register. The reset val-

ue is 000b (blanking window off).

The Current feedback filter sets the number of

consecutive valid samples (when current is above

the limit) needed to generate the active CL event

used to turn OFF the PWM. The reset value is 1.

The sampling of the current comparator is done at

fPERIPH/4.

Table 45. Current Feedback Filter Setting

The ON time of the resulting PWM starts at the

end of the measurement window (rising edge),

and ends either at the beginning of the next meas-

urement window (falling edge), or when the cur-

rent level is reached.

Note: Be careful that the current comparator is

OFF until the CKE and/or DAC bits are set in the

MCRA register.

CFW2 CFW1 CFW0 Blanking window length

0 0 0 Blanking window off

001 0.5 µs

010 1 µs

011 1.5 µs

100 2 µs

101 2.5 µs

110 3 µs

111 3.5 µs

CFF2 CFF1 CFF0 Nb of Feedback Samples

needed to turn OFF PWM

000 1

001 2

010 3

011 4

100 5

101 6

110 7

111 8

LEGEND

ST7MC1xx/ST7MC2xx

188/309

MOTOR CONTROLLER (Cont’d)

10.6.8.5 Current feedback amplifier

In both current and voltage mode, the current

feedback from the motor can be amplified before

entering the comparator. This is done by an inte-

grated Op-amp that can be used when the OAON

bit is set in the OACSR register and the CFAV bit

in the MREF register is reset. This allows the three

points of the Op-amp to be accessed for a pro-

grammable gain. The CFAV bit in the MREF regis-

ter selects the MCCFI0 or OAZ(MCCFI1) pin as

the comparator input as shown in the following ta-

ble.

Table 46. Comparator input selection

If the amplifier is not used for current feedback, it

can be used for other purposes. In this case, the

OAON bit in the OACSR register and the CFAV bit

in the MREF register both have to be set. This

means that the current feedback has to be on the

MCCFI0 pin to be directly connected to the com-

parator and the OAP, OAN and OAZ (MCCFI1)

pins can be used to amplify another signal. Both

the OAZ(MCCFI1) and MCCFI0 pins can be con-

nected to an ADC entry. See (Figure 106).

Note: The MCCFI0 pin is not available in LQFP32;

SDIP32 and LQFP44 devices. In this case, the

CFAV bit must be reset. The choice to use the Op-

amp or not is made with the OAON bit.

10.6.8.6 Measurement Window

In current mode, the measurement window fre-

quency can be programmed between 390Hz and

50KHz by the means of the SA[3:0] bits in the

MPRSR register.

Note: These frequencies are given for a 4 MHz

peripheral input frequency for a BLDC drive

(XT16, XT8 bits in MCONF register).

In sensorless mode this measurement window can

be used to detect BEMF zero crossing events. Its

width can be defined between 2.5μs and 40μs as a

minimum in sensorless mode by the OT[3:0] bits in

the MPWME register.

Figure 106. Current Feedback

CFAV bit Meaning

0 Select OAZ(MCCFI1) as the current

comparator input

1Select MCCFI0 as the current compara-

tor input

OAZ

Filter

VCREF

12-Bit PWM generator

MCCREF

CEXT VCREF MAX = VDD

Power down mode

To Phase State

CFW[2:0] bits

Control

(V)

R1ext

R2ext

VDD

(I)

LEGEND:

(I): Current mode

(V): Voltage mode

CLI: Current limitation inter-

rupt

OAON bit

OACSR

12-bit PWM generator/Compare U

Sampling frequency

V0C1 bit

MCRA Register

Internal clock

MCFR register

OAN

OAP

MCPWMU/V/W

PWME[U:V:W] bit

MREF Register

MCCFI0

CFAV bit

MREF

ADC

CLI

CFF[2:0] bits

MCFR register

(MCCFI1)

ST7MC1xx/ST7MC2xx

189/309

MOTOR CONTROLLER (Cont’d)

This sets the minimum off time of the PWM signal

generated by this internal clock. This off time can

vary depending on the output of the current feed-

back comparator. In sensor mode (SR=1) and

when the sampling for the Z event is done during

the PWM ON time in sensorless mode (SPLG bit is

set in MCRC register and /or DS[3:0] bits with a

value other than 000 in MCONF register), there is

no minimum OFF time required anymore, the min-

imum off time is set automatically to 0µs and the

OFF time of the PWM signal is controlled only by

the current regulation loop.

Table 47. Sampling Frequency Selection

Note: Times are indicated for 4 MHz fPERIPH

Warning: If the off time value set is superior than

the period of the PWM signal (for example 40µs off

time for a 50KHz (25µs period) PWM frequency),

then the signal output on MCOx pins selected is a

100% duty cycle signal (always at 1).

Table 48. Off time table

Note: Times are indicated for 4 MHz fPERIPH

Figure 107. Sampling clock generation block

SA3 SA2 SA1 SA0 Sampling Frequency

0 0 0 0 50.0 KHz

0 0 0 1 40.0 KHz

0 0 1 0 33.33 KHz

0 0 1 1 25.0 KHz

0 1 0 0 20.0 KHz

0 1 0 1 18.1 KHz

0 1 1 0 15.4 KHz

0 1 1 1 12.5 KHz

1000 10 KHz

1 0 0 1 6.25 KHz

1 0 1 0 3.13 KHz

1 0 1 1 1.56 KHz

1 1 0 0 1.25 KHz

1 1 0 1 961 Hz

1 1 1 0 625 Hz

1 1 1 1 390 Hz

OT3 OT2 OT1 OT0

Off Time sen-

sorless mode

(SR=0)

(DS[3:0]=0)

Sensor Mode

(SR=1) or sam-

pling during ON

time in sensor-

less (SPLG =1

and/or DS[3:0]

bits)

0 0 0 0 2.5 µs

No minimum off

time

0 0 0 1 5 µs

0 0 1 0 7.5 µs

0 0 1 1 10 µs

01 0 0 12.5 µs

0 1 0 1 15 µs

01 1 0 17.5 µs

0 1 1 1 20 µs

10 0 0 22.5 µs

1 0 0 1 25 µs

10 1 0 27.5 µs

1 0 1 1 30 µs

1 1 0 0 32.5 μs

1 1 0 1 35 μs

1 1 1 0 37.5 μs

1 1 1 1 40 μs

Frequency logic

fPERIPH

Off-Time logic

SA[3:0] bits

OT[3:0] bits

Toff

Tsampling

Note: The MTC controller input frequency (fPERIPH) is 4 MHz in this example,

MPRSR Register

MPWME Register

It can be configured to 8MHz with the XT16: XT8 bits in the MCONF register

(measurement window)

Sampling

Clock

Frequency

OFF time

The BEMF is sampled at the end of OFF time

in sensorless mode

ST7MC1xx/ST7MC2xx

190/309

MOTOR CONTROLLER (Cont’d)

10.6.9 Channel Manager

The channel manager consists of:

– A Phase State register with preload and polarity

function

– A multiplexer to direct the PWM to the low and/

or high channel group

– A tristate buffer asynchronously driven by an

emergency input

The block diagram is shown in Figure 108.

Figure 108. Channel Manager Block Diagram

CFF[2:0] bits

OO bits*

OE[5:0] bits

6OS[2:0] bits*

Phasen Register*

SR bit

PWM generator

Sampling frequency

DAC bit

Channel [5:0]

Current comparator

output

PWM Generator

V0C1 bit

Filter

OP[5:0] bits

MOE bit

MCO0

MCO1

MCO2

MCO3

MCO4

MCO5

NMCES

MPHST Register

MPOL Register

MCRB Register

MPAR Register

* = Preload register, changes taken into account at next C event.

MCRA Register

MCFR Register

Reg

S,H

events:

Commutation

BEMF

ero-crossing

End Of

emagnetization

Emergency Stop

Notes:

Updated/Shifted on

Ratio Updated (+1 or -1)

Multiplier

verflow

+/-

urrent Mode

oltage Mode

Reg

Updated with Reg

n+1

Branch taken after C event

Branch taken after D event

Channel [5:0]

Dead

Time

Dead

Time

Dead

Time

MDTG Register

High frequency chopper

HFE[1:0] bits

HFRQ[2:0] bits

MREF Register

CLI bit

CLIM bit

OCV bit

OFF time

Sensorless Sensor

Sampling

Clock “1”

ST7MC1xx/ST7MC2xx

191/309

MOTOR CONTROLLER (Cont’d)

10.6.9.1 MPHST Phase State Register

A preload register enables software to asynchro-

nously update the channel configuration for the

next step (during the previous commutation inter-

rupt routine for example): the OO[5:0] bits in the

MPHST register are copied to the Phase register

on a C event.

Table 49. Output State

Direct access to the phase register is also possible

when the DAC bit in the MCRA register is set.

Note: In Direct Access Mode (DAC bit is set in

MCRA register):

1: A C event is generated as soon as there is a

write access to OO[5:0] bits in MPHST register,

2: The PWM application is selected by the OS0 bit

in the MCRB register,

3: Regardless of the value of the CKE bit in the

MCRA register, the MTIM Clock is disabled and D

and Z events are not detected.

Table 50. DAC and MOE Bit Meaning

*Note: The reset state of the outputs can be either

high impedance, low or high state depending on

the corresponding option bit.

The polarity register is used to match the polarity

of the power drivers keeping the same control log-

ic and software. If one of the OPx bits in the MPOL

MCOx is VDD.

Each output status depends also on the momen-

tary state of the PWM, its group (low or high), and

the peripheral state.

PWM Features

The outputs can be split in two PWM groups in or-

der to differentiate the high side and the low side

switches. This output property can be pro-

grammed using the OE[5:0] bits in the MPAR reg-

ister.

Table 51. Meaning of the OE[5:0] Bits

The multiplexer directs the PWM to the upper

channel, the lower channel or both of them alter-

natively or simultaneously according to the periph-

eral state.

This means that the PWM can affect any of the up-

per or lower channels allowing the selection of the

most appropriate reference potential when free-

wheeling the motor in order to:

– Improve system efficiency

– Speed up the demagnetization phase

– Enable Back EMF zero crossing detection.

The OS[2:0] bits in the MCRB register allow the

PWM configuration to be configured for each case

as shown in Figure 110 and Figure 109.

During demagnetization, the OS2 bit is used to

control PWM mode, and it is latched in a preload

event occurs and the configuration is active imme-

diately.

The OS1 bit is used to control the PWM between

the D and Z events to control back-emf detection.

OS0 bit will allow to control the PWM signal be-

tween Z event and next C event.

Note about demagnetization speed-up: during

demagnetization the voltage on the winding has to

be as high as possible in order to reduce the de-

magnetization time. Software can apply a different

PWM configuration on the outputs between the C

and D events, to force the free wheeling on the ap-

propriate diodes to maximize the demagnetization

voltage.

10.6.9.2 Emergency Feature

When the NMCES pin goes low

– The tristate output buffer is put in reset state

asynchronously

– The MOE bit in the MCRA register is reset

– An interrupt request is sent to the CPU if the EIM

bit in the MIMR register is set

This bit can be connected to an alarm signal from

the drivers, thermal sensor or any other security

component.

This feature functions even if the MCU oscillator is

off.

OP[5:0] bit OO[5:0] bit MCO[5:0] Pin

0 0 1 (OFF)

0 1 0-(PWM allowed)

1 0 0 (OFF)

1 1 1-(PWM allowed)

MOE

bit

DAC

bit Effect on Output

0 x Reset state*

10 Standard

running mode

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 74

OE[5:0] Channel group

0 High channel

1 Low channel

@ PWM behaviouraﬂerC 051 PWM behavlouraﬂerD OSO PWM behavmuraﬂerz and before D and before Z and betore nex‘ G <3 4=""> $00 % as $6- 90 o 9 x We HA4— + 4M \ \ \ \ \ \ 5 !—|_l_\_I—Ll—|_Fl l—|_I—|_l—Ll—|_l_\ l—\_I—|_I—Ll—|_l_l Low \ H H \_I—|_l Ll

ST7MC1xx/ST7MC2xx

192/309

MOTOR CONTROLLER (Cont’d)

Figure 109. PWM application in Voltage or Current sensorless mode (see Table 61)

Step

OS2 PWM behaviour after C

High Channels

Low Channels

Voltage (V0C1=x)

Off (0)

On (1)

Cn+1

Mode

OO[5:0]

Demagnetization

Event

OS[2:0]

000 Low

001 High

Low

010

011

High

Low

High

Low

100

101

110

111

OE[5:0]

High

and before D OS1 PWM behaviour after D

High Channels

Low Channels

and before Z

OS0 PWM behaviour after Z

High Channels

Low Channels

and before next C

DemagnetizationDemagnetizationWait Z event Delay

High

Low

High

Low

High

Low

High

Low

OS2 OS1 OS0

052 F'WM behavwour aﬂer C 081 Not Used OSO PWM behaviour alter Z and belore Z and before next C <\ 0="" %="" ﬁe="" ‘="">: 9 . <3. ’="" o="" 9%="" 9="" a4—="" 4="">A<— —="">4 ‘* \ |

ST7MC1xx/ST7MC2xx

193/309

MOTOR CONTROLLER (Cont’d)

Figure 110. PWM application in Voltage or Current Sensor Mode (see Table 62)

Cn+1

Mode

Voltage (V0C1=x)

OS[2:0]

OO[5:0]

(sensor mode: SR=1)

Step

Event

Off (0)

On (1)

0x0

In sensor mode, there is no demagnetisation event and the PWM behaviour can be

changed before and after Z event

OS2 PWM behaviour after C

High Channels

Low Channels

and before Z OS1 Not Used OS0 PWM behaviour after Z

High Channels

Low Channels

and before next C

OS2 OS0

Wait Z event Delay

Delay

OE[5:0]

0x1

1x0

1x1

High

Low

High

Low

High

Low

High

Low

ST7MC1xx/ST7MC2xx

194/309

MOTOR CONTROLLER (Cont’d)

10.6.9.3 Dead Time Generator

When using typical triple half bridge topology for

power converters, precautions must be taken to

avoid short circuits in half bridges. This is ensured

by driving high and low side switches with comple-

mentary signals and by managing the time be-

tween the switching-off and the switching-on in-

stants of the adjacent switches.

This time is usually known as deadtime and has to

be adjusted depending on the devices connected

to the PWM outputs and their characteristics (in-

trinsic delays of level-shifters, delays due to power

switches,...).

When driving motors in six-step mode, the dead-

time generator function also allows synchronous

rectification to be performed on the switch adja-

cent to the one where PWM is applied to reduce

conduction losses.

For each of the three PWM channels, there is one

6-bit Dead Time generator available.

It generates two output signals: A and B.

The A output signal is the same as the input phase

signal except for the rising edge, which is delayed

relative to the input signal rising edge.

The B output signal is the opposite of the input

phase signal except the rising edge which is de-

layed relative to the input signal falling edge.

Figure 111 shows the relationship between the

output signals of the deadtime register and its in-

puts.

If the delay is greater than the width of the active

phase (A or B) then the corresponding pulse is not

generated (see Figure 112 and Figure 113).

Figure 111. Dead Time waveforms

Figure 112. Dead time waveform with delay greater than the negative PWM pulse

Reference

Output A

Output B

Delay

Input signal

Input

Output A

Output B

Delay

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 113. Dead Time waveform with delay greater than the positive PWM pulse

Table 52. Dead time programming and example

The deadtime delay is the same for each of the

channels and is programmable with the DTG[5..0]

bits in the MDTG register.

The resolution is variable and depends on the

DTG5 and DTG4 bits. Table 52 summarizes the

set-up of the deadtime generator.

ITmtc is the period of the Dead Time Generator in-

put clock (Fmtc = 16 MHz in most cases, not affect-

ed by the XT16:XT8 prescaler bits in the MCONF

For safety reasons and since the deadtime de-

pends only on external component characteristics

(level-shifter delay, power components switching

duration,...) the register used to set-up deadtime

duration can be written only once after the MCU

reset. This prevents a corrupted program counter

modifying this system critical set-up, which may

cause excessive power dissipation or destructive

shoot-through in the power stage half bridges.

When using the three independent U, V and W

PWM signals (PCN bit set) (see Figure 114) to

drive the MCOx outputs, deadtime is added as

shown in Figure 111.

The dead time generator is enabled/disabled us-

ing the DTE bit.

The effect of the DTE bit depends on the PCN bit

value.

If the PCN bit is set:

■DTE is read only. To reset it, first reset the PCN

bit, then reset DTE and set PCN to 1 again.

■If DTE=0, the high and low side outputs are

simply complemented (no deadtime insertion,

DTG[5:0] bits are not significant); this is to allow

the use of an external dead time generator.

Note: The reset value of the MDTG register is FFh

so when configuring the dead time, it is mandatory

to follow one the two following sequences:

■To use dead t imes while the PCN bit is set; from

reset state write the MDTG value at once. The

DTE bit will be read back as 1 whatever the

programming value (read only if PCN=1)

■To use dead times while the PCN bit is reset,

write first the dead time value in DTG[5:0], then

reset the PCN bit, or do both actions at the same

time.

DTG5 DTG4 Tdtg Deadtime expression Deadtime value Tdtg

@16MHz Fmtc

Dead time range

@ 16MHz Fmtc

0X2xT

mtc (DTG[4..0]+1) x Tdtg From 1 to 32 Tdtg 125ns 0.125µs to 4µs

104xT

mtc (DTG[3..0]+17) x Tdtg From 17 to 32 Tdtg

250ns 4.25µs to 8µs

118xT

mtc 500ns 8.5µs to 16µs

Input

Output A

Output B

Delay

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 114. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals

Note: The output of the current limitation comparator can be used when 3 PWM signals are enabled if the

VOC1 bit =0 in the MCRA register.

Dead

Time

Dead

Time

Dead

Time

8MDTG Register

UVW

PWM generator signals

PCN bit = 1

OP[5:0] bits

MOE bit

MCO0

MCO1

MCO2

MCO3

MCO4

MCO5

NMCES

MPOL Register

MRCA Register

Channel [1:0]Channel [3:2]Channel [5:4]

High frequency chopper

HFE[1:0] bits

HFRQ[2:0] bits

MREF Register

CLI bit

CLIM bit

OCV bit

regws‘

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MOTOR CONTROLLER (Cont’d)

If the PCN bit is reset, one of the three PWM sig-

nals (the one set by the compare U register pair) or

the output of the measurement window generator

(depending on if the driving mode is voltage or cur-

rent) is used to provide six-step signals through

the PWM manager (to drive a PM BLDC motor for

instance).

In that case, DTE behaves like a standard bit (with

multiple write capability). When the deadtime gen-

erator is enabled (bit DTE=1), some restrictions

are applied, summarized in Table 53:

■Channels are now grouped by pairs:

Channel[0:1], Channel[2:3], Channel[4:5]; a

deadtime generator is allocated to each of these

pairs (see cautions below);

■The input signal of the deadtime generator is the

active output of the PWM manager for the

corresponding channel. For instance, if we

consider the Channel[0:1] pair, it may be either

Channel0 or Channel1.

■When both channels of a pair are inactive, the

corresponding outputs will also stay inactive

(this is mandatory to allow BEMF zero-crossing

detection).

Table 53 summarizes the functionality of the dead-

time generator when the PCN bit is reset. 1(pwm*)

means that the corresponding channel is active (1

in the corresponding bit in the MPHST register),

and a PWM signal is applied on it (using the MPAR

PWM represents the complementary signals (al-

though the duty cycle is slightly different due to

deadtime insertion). 0 means that the channel is

inactive and 1 means that the channel is active

and a logic level 1 is applied on it (no PWM signal).

Table 53. Dead Time generator outputs

* PWM generation enabled

Warning: Grouping channels by pairs imposes the

external connections between the MCO outputs

and power devices; the user must therefore pay at-

tention to respect the “recommended schematics”

described in Figure 123. on page 228 and Figure

124

Note: As soon as the channels are grouped in

pairs, special care has to be taken in configuring

the MPAR register for a PM BLDC drive. If both

channels of the same pair are both labelled “high”

for example and if the PWM is applied on high

channels, the active MCO output x (OOx=1 bit in

the MPHST register) outputs PWM and the paired

MCO output x+1 (OOx+1bit in the MPHST regis-

ter) outputs PWM and vice versa.

Caution: When PCN=0 and a complementary

PWM is applied (DTE=1) on one channel of a pair,

if both channels are active, this corresponds in

output to both channels OFF. This is for security

purpose to avoid cross-conduction.

Caution: To clear the DTE bit from reset state of

MDTG register (FFh), the PCN bit must be cleared

before.

PCN = 0; DTE =1; x= 0, 2, 4

On/Off x

(OOx bit)

On/Off x+1

(OOx+1 bit) MCOx output MCOx+1

output

01 (pwm*)PWM PWM

1 (pwm*) 0 PWM PWM

11 (pwm*) 0 0

1 (pwm*) 1 0 0

10 1 0

01 0 1

00 0 0

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MOTOR CONTROLLER (Cont’d)

Figure 115. Channel Manager Output Block Diagram with PWM generator delivering 1 PWM signal

Dead

Time

Dead

Time

Dead

Time

8MDTG Register

Ch0Ch1Ch2Ch3Ch4Ch5

PCN bit = 0

OP[5:0] bits

MOE bit

MCO0

MCO1

MCO2

MCO3

MCO4

MCO5

MCES

MPOL Register

MCRA Register

Channel [1:0]Channel [3:2]Channel [5:4]

Phasen Register*

PWM generator

Sampling frequency

ISQ

U channel

High frequency chopper

OE[5:0] bits 6

MPAR Register

HFE[1:0] bits

HFRQ[2:0] bits

MREF Register

Current comparator

output

CLI bit

CLIM bit

OCV bit

OFF time

Sensorless Sensor

Sampling

Clock “1”

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.9.4 Programmable Chopper

Depending on the application hardware (use of a

pulse transformer, for example), a chopper may be

needed for the PWM signal. The MREF register al-

lows the chopping frequency and mode to be pro-

grammed.

The HFE[1:0] bits program the channels on which

chopping is to be applied. The chopped PWM sig-

nal may be needed for high side switches only, low

side switches or both of them in the same time

(see Table 54).

Table 54. Chopping mode

The chopping frequency can any of the 8 values

from 100KHz to 2MHz selected by the HFRQ[2:0]

bits in the MREF register (see Table 55).

Table 55. Chopping frequency

Note: When the PCN bit = 0:

– If complementary PWM signals are not applied

(DTE bit = 0), the high and low drivers are fixed

by the MPAR register. Figure 108, Figure 114

and Figure 115 indicate where the HFE[1:0] bits

are taken into account depending on the PWM

application.

– If complementary PWM signals are applied (DTE

bit = 1), the channels are paired as explained in

“Dead Time Generator” on page 194. This

means that the high and low channels are fixed

and the HFE[1:0] bits indicate where to apply the

chopper. Figure 116 shows typical complemen-

tary PWM signals with high frequency chopping

enabled on both high and low drivers.

Figure 116. Complementary PWM signals with chopping frequency on high and low side drivers

HFE[1:0] bits Chopping mode

HFE1 HFE0 PCN bit =0 PCN bit =1

00 OFF OFF

0 1 Low channels only Low side switches

MCO1, 3, 5

1 0 High channels only High side switches

MCO0, 2, 4

Both Low and High

channels

Both high and low

sides

HFRQ2 HFRQ1 HFRQ0

Chopping

frequency

Fmtc = 16MHz

Fmtc = 8MHz

Chopping

frequency

Fmtc = 4MHz

0 0 0 100 KHz 50 KHz

0 0 1 200 KHz 100 KHz

0 1 0 400 KHz 200 KHz

0 1 1 500 KHz 250 KHz

1 0 0 800 KHz 400 KHz

1 0 1 1 MHz 500 KHz

1 1 0 1.33 MHz 666.66 MHz

1112 MHz 1 MHz

Reference

Output A

Output B

Delay

Input signal

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.10 PWM Generator Block

The PWM generator block produces three inde-

pendent PWM signals based on a single carrier

frequency with individually adjustable duty cycles.

Depending on the motor driving method, one or

three of these signals may be redirected to the oth-

er functional blocks of the motor control peripheral,

using the PCN bit in the MDTG register.

When driving PM BLDC motors in six-step mode

(voltage mode only, either sensored or sensor-

less) a single PWM signal (Phase U) is used to

supply the Input Stage, PWM and Channel Man-

ager blocks according to the selected modes.

For other kind of motors requiring independent

PWM control for each of the three phases, all

PWM signals (Phases U, V and W) are directed to

the channel manager, in which deadtime or a high

frequency carrier may be added. This is the case

of AC induction motors or PMAC motors for in-

stance, supplied with 120° shifted sinewaves in

voltage mode.

10.6.10.1 Main Features

■12-bit PWM free-running Up/Down Counter with

up to 16MHz input clock (Fmtc).

■Edge-aligned and center-aligned PWM

operating modes

■Possibility to re-load compare registers twice

per PWM period in center-aligned mode

■Full-scale PWM generation

■PWM update interrupt generation

■8-bit repetition counter

■8-bit PWM mode

■Timer re-synchronisation feature

Figure 117. PWM generator block diagram

MREP Register

12-bit Compare 0 Register

12-bit PWM Counter

13-bit Compare W Register

Up to 16MHz CMS bit

13-bit Compare U Register

13-bit Compare V Register

Clear or Up/Down

Prescaler

PCP[2:0] bits

Reg

event:

Update of compare registers

Notes:

Preload registers transferred

to active registers on U event

Fmtc

MPCR Register MPCR Register

PWM interrupt generation

Repetition

counter

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.10.2 Functional Description

The 3 PWM signals are generated using a free-

running 12-bit PWM Counter and three 13-bit

Compare registers for phase U, V and W: MCM-

PU, MCMPV and MCMPW registers.

A fourth 12-bit register is needed to set-up the

PWM carrier frequency: MCMP0 register.

Each of these compare registers is buffered with a

preload register. Transfer from preload to active

registers is done synchronously with PWM counter

underflow or overflow depending on configuration.

This allows to write compare values without risks

of spurious PWM transitions.

The block diagram of the PWM generator is shown

on Figure 117.

10.6.10.3 Prescaler

The 12-bit PWM Counter clock is supplied through

a 3-bit prescaler to allow the generation of lower

PWM carrier frequencies. It divides Fmtc by 1, 2, 3,

..., 8 to get Fmtc-pwm.

This prescaler is accessed through three bits

PCP[2:0] in MPCR register; this register is buff-

ered: the new value is taken into account after a

PWM update event.

10.6.10.4 PWM Operating mode

The PWM generator can work in center-aligned or

edge-aligned mode depending on the CMS bit set-

ting in the MPCR register.

Figure 118 shows the corresponding counting se-

quence .

It offers also an 8-bit mode to get a full 8-bit range

with a single compare register write access by set-

ting the PMS bit in MPCR register.

The comparisons described here are performed

between the PWM Counter value extended to 13

bits and the 13-bit Compare register. Having a

compare range greater than the counter range is

mandatory to get a full PWM range (i.e. up to

100% modulation). This principle is maintained for

8-bit PWM operations.

■Center-aligned Mode (CMS bit = 1)

In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare 0 reg-

ister then counts down until it reaches zero and re-

starts counting up.

The PWM signals are set to ‘0’ when the PWM

Counter reaches, in up-counting, the correspond-

ing 13-bit Compare register value and they are set

to ‘1’ when the PWM Counter reaches the 13-bit

Compare value again in down-counting.

Figure 118. Counting sequence in center-aligned and edge-aligned mode

center-aligned

mode 0 1 2 .... 15 16 15 .... 2 1 0 1

edge-aligned

mode 0 1 2 ..... 15 16 0 1 ..... 16 0 1

T = PWM period, Value of 12-bit Compare 0 Register= 16

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

If the 13-bit Compare register value is greater than

the extended Compare 0 Register (the 13th bit is

set to ‘0’), the corresponding PWM output signal is

held at ‘1’.

If the 13-bit Compare register value is 0, the corre-

sponding PWM output signal is held at ‘0’.

Figure 119 shows some center-aligned PWM

waveforms in an example where the Compare 0

Figure 119. Center-aligned PWM Waveforms (Compare 0 Register = 8)

012345678765432101

3‘1’

4‘0’

1 Compare Register value = 4

2 Compare Register value = 7

3 Compare Register value > = 8

4 Compare Register value = 0

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

■Edge-aligned Mode (CMS bit = 0)

In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare Reg-

ister. Then the PWM Counter is cleared and it re-

starts counting up.

The PWM signals are set to ‘0’ when the PWM

Counter reaches, in up-counting, the correspond-

ing 13-bit Compare register value and they are set

to ‘1’ when the PWM Counter is cleared.

If the 13-bit Compare register value is greater than

the extended Compare 0 register (the 13th bit is

set to ‘0’), the corresponding PWM output signal is

held at ‘1’.

If the 13-bit Compare register value = 0, the corre-

sponding PWM output signal is held at ‘0’.

Figure 120 shows some edge-aligned PWM wave-

forms in an example where the Compare 0 register

value = 8.

Figure 120. Edge-aligned PWM Waveforms (Compare 0 Register = 8)

01234567801

3‘1’

4‘0’

1 Compare Register value = 4

2 Compare Register value = 8

3 Compare Register value > 8

4 Compare Register value = 0

MPO

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

■12-bit Mode (PMS bit = 0 in the MPCR register)

This mode is useful for MCMP0 values ranging

from 9 bits to 12 bits. Figure 121 presents the way

Compare 0 and Compare U, V, W should be load-

ed). It requires loading two bytes in the MCMPxH

and MCMPxL registers (i.e. MCMP0, MCMPU,

MCMPV and MCMPW 16-bit registers) following

the sequence described below:

– write to the MCMPxL register (LSB) first

– then write to the MCMPxH register (MSB).

The 16-bit value is then ready to be transferred in

the active register as soon as an update event oc-

curs. This sequence is necessary to avoid poten-

tial conflicts with update interrupts causing the

hardware transfer from preload to active registers:

if an update event occurs in the middle of the

above sequence, the update is effective only when

the MSB has been written.

■8-bit PWM mode (PMS bit = 1 in MPCR register)

This mode is useful whenever the MCMP0 value is

less or equal to 8-bits. It allows significant CPU re-

source savings when computing three-phase duty

cycles during PWM interrupt routines. In this

mode, the Compare 0 and Compare U, V, W reg-

isters have the same size (8 bits). The extension of

the MCMPx registers is done in using the OVFx

bits in the MPCR register (refer to Figure 121).

These bits force the related duty-cycles to 100%

and are reset by hardware on occurence of a

PWM update event.

Note about read access to registers with

preload: during read accesses, values read are

the content of the preload registers, not the active

registers.

Note about compare register active bit loca-

tions: the 13 active bits of the MCMPx registers

are left-aligned. This allows temporary calculations

to be done with 16-bit precision, round-up is done

automatically to the 13-bit format when loading the

values of the MCMPx registers.

Note about MCMP0x registers: the configuration

MCMP0H=MCMP0L=0 is not allowed

Figure 121. Comparison between 12-bit and 8-bit PWM mode

OvfX

MCMP0H

MCMP0L

MCMPxH

MCMPxL

Ext

MCMP0H

MCMP0L

MCMPxH

MCMPxL

MPCR

12-bit PWM mode

(PMS bit = 0)

8-bit PWM mode

(PMS bit = 1)

OvfWOvfVOvfU

Ext

Bit not available

Bit extending comparison range

Equivalent bit location

PWM frequency

set-up

Phase x duty

cycle set-up

PWM frequency

set-up

Phase x duty

cycle set-up

\AA/WW W V. +++++++++++++ +++++++++++++ w+¢+¢+¢+¢+¢+¢+ + + + + + + + WWW MAW/WWW ﬁ++++++++ 94 E]

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.10.5 Repetition Down-Counter

Both in center-aligned and edge-aligned modes,

the four Compare registers (one Compare 0 and

three for the U, V and W phases) are updated

when the PWM counter underflow or overflow and

the 8-bit Repetition down-counter has reached ze-

ro.

This means that data are transferred from the

preload compare registers to the compare regis-

ters every N cycles of the PWM Counter, where N

is the value of the 8-bit Repetition register in edge

-aligned mode. When using center-aligned mode,

the repetition down-counter is decremented every

time the PWM counter overflows or underflows. Al-

though this limits the maximum number of repeti-

tion to 128 PWM cycles, this makes it possible to

update the duty cycle twice per PWM period. As a

result, the effective PWM resolution in that case is

equal to the resolution we can get using edge-

aligned mode, i.e. one Tmtc period. When refresh-

ing compare registers only once per PWM period

in center-aligned mode, maximum resolution is

2xTmtc , due to the symmetry of the pattern.

The repetition down counter is an auto-reload

type; the repetition rate will be maintained as de-

fined by the MREP register value (refer to Figure

122).

10.6.10.6 PWM interrupt generation

A PWM interrupt is generated synchronously with

the “U” update event, which allows to refresh com-

pare values by software before the next update

event. As a result, the refresh rate for phases duty

cycles is directly linked to MREP register setting.

A signal reflecting the update events may be out-

put on a standard I/O port for debugging purposes.

Refer to section10.6.7.3 on page 172 for more de-

tails.

Figure 122. Update rate examples depending on mode and MREP register settings

Center-aligned mode Edge-aligned mode

UU Event: Preload registers transferred to active registers and PWM interrupt generated

12-bit PWM

Counter

MREP = 0

MREP = 1

MREP = 2

MREP = 3

U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal

to MCP0.

MREP = 3

and

re-synchronization

(by SW) (by SW)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.10.7 Timer Re-synchronisation

The 12-bit timer can be re-synchronized by a sim-

ple write access with FFh value in the MISR regis-

ter. Re-synchronization means that the 12-bit

counter is reset and all the compare preload regis-

ters MCP0, MCPU, MCPV, MCPW are transferred

to the active registers.

To re-synchronize the 12-bit timer properly , the

following procedure must be applied:

– 1. Load the new values in the preload compare

registers

– 2. Load FFh value in the MISR register (this will

reset the counter and transfer the compare

preload registers in the active registers: U event)

– 3. Reset the PUI flag by loading 7Fh in the MISR

Note: Loading FFh value in the MISR register will

have no effect on any other flag than the PUI flag

and will generate a PWM update interrupt if the

PUM bit is set.

Warning: In switched mode (SWA bit is reset), the

procedure is the same and loading FFh in the

MISR register will have no effect on flags except

on the PUI flag. As a consequence, it is recom-

mended to avoid setting RMI and RPI flags at the

same time in switched mode because none of

them will be taken into account.

10.6.10.8 PWM generator initialization and

start-up

The three-phase generator counter stays in reset

state (i.e. stopped and equal to 0), as long as MTC

peripheral clock is disabled (CKE = 0).

Setting the CKE bit has two actions on the PWM

generator:

■It starts the PWM counter

■It forces the update of all registers with preload

registers transferred on U update event, i.e.

MREP, MPCR, MCMP0, MCMPU, MCMPV,

MCMPW (in 12-bit mode, both MCMPxL and

MCMPxH must have been written, following the

mandatory LSB/MSB sequence, before setting

CKE bit). It consequently generates a U

interrupt.

10.6.11 Low Power Modes

Before executing a HALT or WFI instruction, soft-

ware must stop the motor, and may choose to put

the outputs in high impedance.

10.6.12 Interrupts

The MTC interrupt events are connected to the

three interrupt vectors (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

Mode Description

Wait No effect on MTC interface.

MTC interrupts exit from Wait mode.

Halt

MTC registers are frozen.

In Halt mode, the MTC interface is in-

active. The MTC interface becomes

operational again when the MCU is

woken up by an interrupt with “exit

from Halt mode” capability.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Ratio increment RPI RIM Yes No

Ratio decrement RMI Yes No

Speed Error SEI SEM Yes No

Emergency Stop EI EIM Yes No

Current Limitation CLI CLIM Yes No

BEMF Zero-Crossing ZI ZIM Yes No

End of Demagnetization DI DIM Yes No

Commutation or

Capture CI CIM Yes No

PWM Update PUI PUM Yes No

Sampling Out SOI SOM Yes Not

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

10.6.13 Register Description

TIMER COUNTER REGISTER (MTIM)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = T[7:0]: MTIM Counter Value.

These bits contain the current value of the 8-bit up

counter. In Speed Measurement Mode, when us-

ing Encoder sensor and MTIM captures triggered

by SW (refer to Figure 102) a read access to MTIM

TIMER COUNTER REGISTER LSB (MTIML)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = TL[7:0]: MTIM Counter Value LSB.

These bits contain the current value of the least

significant byte of the MTIM up counter, when

used in Speed Measurement Mode (i.e. as a 16-bit

timer)

CAPTURE Zn-1 REGISTER (MZPRV)

Read /Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = ZP[7:0]: Previous Z Value or Speed

capture LSB.

These bits contain the previous captured BEMF

value (ZN-1) in Switched and Autoswitched mode

or the LSB of the captured value of the

[MTIM:MTIML] registers in Speed Sensor Mode.

CAPTURE Zn REGISTER (MZREG)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = ZC[7:0]: Current Z Value or Speed cap-

ture MSB.

These bits contain the current captured BEMF val-

ue (ZN) in Switched and Autoswitched mode or the

MSB of the captured value of the [MTIM:MTIML]

registers in Speed Sensor Mode. A read access to

MZREG in this case disable the Speed captures

up to MZPRV reading (refer to Section 10.6.7.5

Speed Measurement Mode on page 180).

COMPARE Cn+1 REGISTER (MCOMP)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DC[7:0]: Next Compare Value.

These bits contain the compare value for the next

commutation (CN+1).

DEMAGNETIZATION REGISTER (MDREG)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = DN[7:0]: D Value.

These bits contain the compare value for simulat-

ed demagnetization (DN) and the captured value

for hardware demagnetization (DH) in Switched

and Autoswitched mode.

In Speed Sensor Mode, the register contains the

value used for comparison with MTIM registers to

generate a Speed Error event.

76543210

T7 T6 T5 T4 T3 T2 T1 T0

76543210

TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0

76543210

ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 ZP0

76543210

ZC7 ZC6 ZC5 ZC4 ZC3 ZC2 ZC1 ZC0

76543210

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

76543210

DN7 DN6 DN5 DN4 DN3 DN2 DN1 DN0

ST7MC1xx/ST7MC2xx

208/309

MOTOR CONTROLLER (Cont’d)

AN WEIGHT REGISTER (MWGHT)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = AN[7:0]: A Weight Value.

These bits contain the AN weight value for the mul-

tiplier. In autoswitched mode the MCOMP register

is automatically loaded with:

when a Z event occurs.

(*) depending on the DCB bit in the MCRA regis-

ter.

PRESCALER & SAMPLING REGISTER

(MPRSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:4 = SA[3:0]: Sampling Ratio.

These bits contain the sampling ratio value for cur-

rent mode. Refer to Table 47, “Sampling Frequen-

cy Selection,” on page 189.

Bits 3:0 = ST[3:0]: Step Ratio.

These bits contain the step ratio value. It acts as a

prescaler for the MTIM timer and is auto incre-

mented/decremented with each R+ or R- event.

Refer to Table 40, “Step Frequency/Period Range

(4MHz),” on page 179 and Table 41, “Modes of

Accessing MTIM Timer-Related Registers,” on

page 179.

INTERRUPT MASK REGISTER (MIMR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PUM: PWM Update Mask bit.

0: PWM Update interrupt disabled

1: PWM Update interrupt enabled

Bit 6 = SEM: Speed Error Mask bit.

0: Speed Error interrupt disabled

1: Speed Error interrupt enabled

Bit 5 = RIM: Ratio update Interrupt Mask bit.

0: Ratio update interrupts (R+ and R-) disabled

1: Ratio update interrupts (R+ and R-) enabled

Bit 4 = CLIM: Current Limitation Interrupt Mask bit.

0: Current Limitation interrupt disabled

1: Current Limitation interrupt enabled

This interrupt is available only in Voltage Mode

(VOC1 bit=0 in MCRA register) and occurs when

the Motor current feedback reaches the external

current limitation value.

Bit 3 = EIM: Emergency stop Interrupt Mask bit.

0: Emergency stop interrupt disabled

1: Emergency stop interrupt enabled

Bit 2 = ZIM: Back EMF Zero-crossing Interrupt

Mask bit.

0: BEMF Zero-crossing Interrupt disabled

1: BEMF Zero-crossing Interrupt enabled

Bit 1 = DIM: End of Demagnetization Interrupt

Mask bit.

0: End of Demagnetization interrupt disabled

1: End of Demagnetization interrupt enabled if the

HDM or SDM bit in the MCRB register is set

Bit 0 = CIM: Commutation / Capture Interrupt

Mask bit

0: Commutation / Capture Interrupt disabled

1: Commutation / Capture Interrupt enabled

76543210

AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

76543210

SA3 SA2 SA1 SA0 ST3 ST2 ST1 ST0

Zn x MWGHT

256(d) or ZN-1 x MWGHT

256(d) (*)

76543210

PUM SEM RIM CLIM EIM ZIM DIM CIM

ST7MC1xx/ST7MC2xx

209/309

MOTOR CONTROLLER (Cont’d)

INTERRUPT STATUS REGISTER (MISR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PUI: PWM Update Interrupt flag.

This bit is set by hardware when all the PWM

Compare register are transferred from the preload

to the active registers. The corresponding interrupt

allows the user to refresh the preload registers be-

fore the next PWM update event defined with

MREP register.

0: No PWM Update interrupt pending

1: PWM Update Interrupt pending

Bit 6 = RPI: Ratio Increment interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R+ interrupt pending

1: R+ Interrupt pending

Switched mode (SWA bit =0):

0: No R+ action

1: The hardware will increment the ST[3:0] bits

when the next commutation occurs and shift all

timer registers right.

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R+ interrupt pending

1: R+ Interrupt pending

Bit 5 = RMI: Ratio Decrement interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R- interrupt pending

1: R- Interrupt pending

Switched mode (SWA bit =0):

0: No R- action

1: The hardware will decrement the ST[3:0] bits

when the next commutation occurs and shift all

timer registers left.

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R- interrupt pending

1: R- Interrupt pending

Bit 4 = CLI: Current Limitation interrupt flag.

0: No Current Limitation interrupt pending

1: Current Limitation interrupt pending

Bit 3 = EI: Emergency stop Interrupt flag.

0: No Emergency stop interrupt pending

1: Emergency stop interrupt pending

Bit 2 = ZI: BEMF Zero-crossing interrupt flag.

0: No BEMF Zero-crossing Interrupt pending

1: BEMF Zero-crossing Interrupt pending

Bit 1 = DI: End of Demagnetization interrupt flag.

0: No End of Demagnetization interrupt pending

1: End of Demagnetization interrupt pending

Bit 0 = CI: Commutation / Capture interrupt flag

0: No Commutation / Capture Interrupt pending

1: Commutation / Capture Interrupt pending

Note 1: Loading value FFh in the MISR register

will reset the PWM generator counter and transfer

the compare preload registers in the active regis-

ters by generating a U event (PUI bit set to 1). Re-

fer to “Timer Re-synchronisation” on page 206.

Note 2: When several MTC interrupts are enabled

at the same time the BRES instruction must not be

used to avoid unwanted clearing of status flags: if

a second interrupt occurs while BRES is executed

(which performs a read-modify-write sequence) to

clear the flag of a first interrupt, the flag of the sec-

ond interrupt may also be cleared and the corre-

sponding interrupt routine will not be serviced. It is

thus recommended to use a load instruction to

clear the flag, with a value equal to the logical

complement of the bit. For instance, to clear the

PUI flag:

ld MISR, # 0x7F.

Note 3: In Autoswitched mode (SWA=1 in the

MRCA register): As all bits in the MISR register are

status flags, they are set by internal hardware sig-

nals and must be cleared by software. Any attempt

to write them to 1 will have no effect (they will be

read as 0) without interrupt generation.

In Switched mode (SWA=0 in the MRCA regis-

ter):

To avoid any losing any interrupts when modifying

the RMI and RPI bits the following instruction se-

quence is recommended:

ld MISR, # 0x9F ; reset both RMI & RPI bits

ld MISR, # 0xBF ; set RMI bit

ld MISR, # 0xDF ; set RPI bit

76543210

PUI RPI RMI CLI EI ZI DI CI

ST7MC1xx/ST7MC2xx

210/309

MOTOR CONTROLLER (Cont’d)

CONTROL REGISTER A (MCRA)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MOE: Output Enable bit.

0: Outputs disabled

1: Outputs enabled

Notes:

– The reset state is either high impedance, high or

low state depending on the corresponding option

bit.

– When the MOE bit in the MCRA register is reset

(MCOx outputs in reset state), and the SR bit in

the MCRA register is reset (sensorless mode)

and the SPLG bit in the MCRC register is reset

(sampling at PWM frequency) then, depending

on the state of the ZSV bit in the MSCR register,

Z event sampling can run or be stopped (and D

event is sampled).

Bit 6 = CKE: Clock Enable Bit.

0: Motor Control peripheral Clocks disabled

1: Motor Control peripheral Clocks enabled

Note: Clocks disabled means that all peripheral in-

ternal clocks (Delay manager, internal sampling

clock, PWM generator) are disabled. Therefore,

the peripheral can no longer detect events and the

preload registers do not operate.

When Clocks are disabled, write accesses are al-

lowed, so for example, MTIM counter register can

be reset by software.

Table 56. Output configuration summary

Note 1: “Peripheral frozen” configuration is not

recommended, as the peripheral may be stopped

in a unknown state (depending on PWM generator

outputs,etc.). It is better practice to exit from run

mode by first setting output state (by toggling ei-

ther MOE or DAC bits) and then to disabling the

clock if needed.

Note 2: In Direct Access Mode (DAC=1), when

CKE=0 (Peripheral Clock disabled) only logical

level can be applied on the MCOx outputs when

they are enabled whereas when CKE=1 (Peripher-

al Clock enabled), a PWM signal can be applied

on them. Refer to Table 74, “DeadTime generator

set-up,” on page 221

Note 3: When clocks are disabled (CKE bit reset)

while outputs are enabled (MOE bit set), the ef-

fects on the MCOx outputs where PWM signal is

applied depend on the running mode selected:

– in voltage mode (VOC1 bit=0), the MCOx out-

puts where PWM signal is applied stay at level 1.

– in current mode (VOC1 bit=1), the MCOx outputs

where PWM signal is applied are put to level 0.

In all cases, MCOx outputs where a level 1 was

applied before disabling the clocks stay at level 1.

That is why it is recommended to disable the

MCOx outputs (reset MOE bit) before disabling the

clocks. This will put all the MCOx outputs under re-

set state defined by the corresponding option bit.

76543210

MOE CKE SR DAC V0C1 SWA PZ DCB

MOE bit MCO[5:0] Output pin

State

0 Reset state

1 Output enabled

CKE

bit

MOE

bit

DAC

bit

Peripheral

Clock

Effect on MCOx

Output

0 0 x Disabled Reset state

0 1 0 Disabled Peripheral frozen (see

note 1 below)

0 1 1 Disabled

Direct access via

MPHST

(only logical level)

1 0 x Enabled Reset state

1 1 0 Enabled Standard

running mode.

1 1 1 Enabled

Direct access via

MPHST (PWM can be

applied)

ST7MC1xx/ST7MC2xx

211/309

MOTOR CONTROLLER (Cont’d)

Effect on PWM generator: the PWM generator

12-bit counter is reset as soon as CKE = 0; this en-

sures that the PWM signals start properly in all

cases. When these bits are set, all registers with

preload on Update event are transferred to active

registers.

Bit 5 = SR: Sensor ON/OFF.

0: Sensorless mode

1: Position Sensor mode

Table 57. Sensor Mode Selection

See also Table 61 and Table 62

Bit 4 = DAC: Direct Access to phase state register.

0: No Direct Access (reset value). In this mode the

preload value of the MPHST and MCRB regis-

ters is taken into account at the C event.

1: Direct Access enabled. In this mode, write a val-

ue in the MPHST register to access the outputs

directly.

Note: In Direct Access Mode (DAC bit is set in

MCRA register), a C event is generated as soon

as there is a write access to the OO[5:0] bits in

MPHST register. In this case, the PWM low/high

selection is done by the OS0 bit in the MCRB

Table 58. DAC Bit Meaning

Bit 3 = V0C1: Voltage/Current Mode

0: Voltage Mode

1: Current Mode

Bit 2 = SWA: Switched/Autoswitched Mode

0: Switched Mode

1: Autoswitched Mode

Note 1 : after reset, in autoswitched mode (SWA

=1) , the motor control peripheral is waiting for a C

commutation event.

Note 2: After reset, a C event is immediately gen-

erated when CKE and SWA are simultaneaously

set due to a nil value of MCOMP.

Bit 1 = PZ: Protection from parasitic Zero-crossing

event detection

0: Protection disabled

1: Protection enabled

Note: If the PZ bit is set, the Z event filter

(ZEF[3:0] in the MZFR register is ignored.

Bit 0 = DCB: Data Capture bit

0: Use MZPRV (ZN-1) for multiplication

1: Use MZREG (ZN) for multiplication

Table 59. Multiplier Result

bit Mode OS[2:0]

bits

Behaviour of the output

PWM

0Sensors

not used

OS[2:0]

bits

enabled

“Between Cn&D” behaviour,

“between D&Z” behaviour

and “between Z&Cn+1” be-

haviour

1Sensors

used

OS1

disabled

“Between Cn&Z” behaviour

and “between Z&Cn+1” be-

haviour

MOE

bit

DAC

bit Effect on Output

Reset state depending on the option

bit

10 Standard

running mode.

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 74

DCB bit Commutation Delay

0 MCOMP = MWGHT x MZPRV / 256

1 MCOMP = MWGHT x MZREG / 256

ST7MC1xx/ST7MC2xx

212/309

MOTOR CONTROLLER (Cont’d)

CONTROL REGISTER B (MCRB)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7= Reserved, must be kept at reset value.

Bit 6= CPB*: Compare Bit for Zero-crossing detec-

tion.

0: Zero crossing detection on falling edge

1: Zero crossing detection on rising edge

Bit 5= HDM*: Hardware Demagnetization event

Mask bit

0: Hardware Demagnetization disabled

1: Hardware Demagnetization enabled

Bit 4= SDM*: Simulated Demagnetization event

Mask bit

0: Simulated Demagnetization disabled

1: Simulated Demagnetization enabled

Bit 3 = OCV: Over Current Handling in Voltage

mode

0: Over Current protection is OFF

1:Over current protection is ON

This bit acts as follows

Table 60. Over current handling

Note 1: This feature is also available when using

the three PWM outputs (PCN bit=1 in the MDTG

Bits 2:0 = OS2*, OS[1:0]: Operating output mode

Selection bits

Refer to the Step behaviour diagrams (Figure 109,

Figure 110) and Table 61, “Step Behaviour/ sen-

sorless mode,” on page 212.

These bits are used to define the various PWM

output configurations.

Note: OS2 is the only preload bit.

Table 61. Step Behaviour/ sensorless mode

Note: For more details, see Step behaviour dia-

grams (Figure 109 and Figure 110).

* Preload bits, new value taken into account at the

next C event. A C event is generated at each write

to MPHST in Direct Access mode.

76543210

0 CPB* HDM* SDM* OCV OS2* OS1 OS0

CLIM bit CLI bit OCV bit Output effect Interrupt

00x

Normal running

mode No

01x

PWM is put off as

Current loop effect No

10x

Normal running

mode No

110

PWM is put off as

Current loop effect Yes

111

All MCOx outputs

are put in reset

state (MOE reset) 1) Yes

OS2

bit

PWM after

C and

before D

OS1

bit

PWM after

D and

before Z

OS0

PWM after

Z and

before next

0On High

Channels

0On High

Channels

0On high

channels

1On low

channels

1On Low

Channels

0On high

channels

1On low

channels

1On Low

Channels

0On High

Channels

0On high

channels

1On low

channels

1On Low

Channels

0On high

channels

1On low

channels

ST7MC1xx/ST7MC2xx

213/309

MOTOR CONTROLLER (Cont’d)

Table 62. PWM mode when SR=1

Table 63. PWM mode when DAC=1

Warning: As the MCRB register contains preload

bits with, it has to be written as a complete byte. A

Bit Set or Bit Reset instruction on a non-preload bit

will have the effect of resetting all the preload bits.

CONTROL REGISTER C (MCRC)

Read/Write (except EDIR bit)

Reset Value: 0000 0000 (00h)

Bit 7= SEI/OI: Speed Error interrupt flag / MTIM

Overflow flag

Position Sensor or Sensorless mode (TES[1:0]

bits =00):

OI: MTIM Overflow flag

This flag signals an overflow of the MTIM timer. It

has to be cleared by software.

0: No MTIM timer overflow

1: MTIM timer overflow

Note: No interrupt is associated with this flag

Speed Sensor mode (TES[1:0] bits =01, 10, 11):

SEI: Speed error interrupt flag

0: No Tacho Error interrupt pending

1: Tacho Error interrupt pending

Bit 6= EDIR/HZ : Encoder Direction bit/ Hardware

zero-crossing event bit

Position Sensor or Sensorless mode (TES[1:0]

bits =00):

HZ: Hardware zero-crossing event bit

This Read/Write bit selects if the Z event is hard-

ware or not.

0: No hardware zero-crossing event

1: Hardware zero-crossing event

Speed Sensor mode (TES[1:0] bits =01, 10, 11):

EDIR:Encoder Direction bit

This bit is Read only. As the rotation direction de-

pends on encoder outputs and motor phase con-

nections, this bit cannot indicate absolute direc-

tion. It therefore gives the relative phase-shift (i.e.

advance/delay) between the two signals in quad-

rature output by the encoder (see Figure 90).

0: MCIA input delayed compared to MCIB input.

1: MCIA input in advance compared to MCIB input

Bit 5 = SZ: Simulated zero-crossing event bit

0: No simulated zero-crossing event

1: Simulated zero-crossing event

Bit 4 = SC: Simulated commutation event bit

0: Hardware commutation event in auto-switched

mode (SWA = 1 in MCRA register)

1: Simulated commutation event in auto-switched

mode (SWA = 1 in MCRA register).

Bit 3 = SPLG: Sampling Z event at high frequency

in sensorless mode (SR=0)

This bit enables sampling at high frequency in sen-

sorless mode independently of the PWM signal or

only during ON time if the DS[3:0] bits in the

MCONF register contain a value. Refer to

Table 77, “Sampling Delay,” on page 224

0: Normal mode (Z sampling at PWM frequency at

the end of the off time)

1: Z event sampled at fSCF (see Table 82)

Note: When the SPLG bit is set, there is no mini-

mum OFF time programmed by the OT [3:0] bits,

the OFF time is forced to 0µs. This means that in

current mode, the OFF time of the PWM signal will

come only from the current loop.

OS2

bit

PWM after

C and

before Z

OS1

bit Unused OS0

PWM after Z

and before

next C

0On High

Channels xx

0On high

channels

1On low

channels

1On Low

Channels xx

0On high

channels

1On low

channels

OS2

bit Unused OS1

bit Unused OS0 PWM on

outputs

xxxx

0On high

channels

1On low

channels

76543210

SEI /

EDIR/

HZ SZ SC SPLG VR2 VR1 VR0

ST7MC1xx/ST7MC2xx

214/309

MOTOR CONTROLLER (Cont’d)

Bits 2:0 = VR[2:0]: BEMF/demagnetisation Refer-

ence threshold

These bits select the Vref value as shown in the

Table 64. The Vref value is used for BEMF and

Demagnetisation detection.

Table 64. Threshold voltage setting

*Typical values for VDD=5V

PHASE STATE REGISTER (MPHST)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS[1:0]*: Input Selection bits

These bits mainly select the input to connect to

comparator as shown in Table 65. The fourth con-

figuration (IS[1:0] = 11) specifies that an incremen-

tal encoder is used (in that case MCIA and MCIB

digital signals are directly connected to the incre-

mental encoder interface and the analog multi-

plexer is bypassed.

Table 65. Input Channel Selection

Bits 5:0 =OO[5:0]*: Channel On/Off bits

These bits are used to switch channels on/off at

the next C event if the DAC bit =0 or directly if

DAC=1

0: Channel Off, the relevant switch is OFF, no

PWM possible

1: Channel On the relevant switch is ON, PWM is

possible (not signifiant when PCN or DTE bit is

set).

Table 66. OO[5:0] Bit Meaning

* Preload bits, new value taken into account at

next C event.

Caution: As the MPHST register contains bits with

preload, the whole register has to be written at

once. This means that a Bit Set or Bit Reset in-

struction on only one bit without preload will have

the effect of resetting all the bits with preload.

VR2 VR1 VR0 Vref voltage threshold

111

Threshold voltage set by ex-

ternal MCVREF pin

1 1 0 3.5V*

101 2.5V*

100 2V*

011 1.5V*

010 1V*

0 0 1 0.6V*

0 0 0 0.2V*

76543210

IS1* IS0* OO5* OO4* OO3* OO2* OO1* OO0*

IS1 IS0 Channel selected

00 MCIA

01 MCIB

10 MCIC

1 1 Both MCIA and MCIB: Encoder Mode

OO[5:0] Output Channel State

0 Inactive

1Active

ST7MC1xx/ST7MC2xx

215/309

MOTOR CONTROLLER (Cont’d)

MOTOR CURRENT FEEDBACK REGISTER

(MCFR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7= RPGS: Register Page Selection:

0: Access to registers mapped in page 0

1: Access to registers mapped in page 1

Bit 6= RST: Reset MTC registers.

Software can set this bit to reset all MTC registers

without resetting the ST7.

0: No MTC register reset

1: Reset all MTC registers

Bits 5:3 = CFF[2:0]: Current Feedback Filter bits

These bits select the number of consecutive valid

samples (when the current is above the limit)

needed to generate the active event. Sampling is

done at fPERIPH/4.

Table 67. Current Feedback Filter Setting

Bits 2:0 = CFW[2:0]: Current Window Filter bits:

These bits select the length of the blanking win-

dow activated each time PWM is turned ON. The

filter blanks the output of the current comparator.

Table 68. Current Feedback Window Setting

Note: Times are indicated for 4 MHz fPERIPH

76543210

RPGS RST CFF2 CFF1 CFF0 CFW2 CFW1 CFW0

CFF2 CFF1 CFF0 Current Feedback Samples

000 1

001 2

010 3

011 4

100 5

101 6

110 7

111 8

CFW2 CFW1 CFW0 Blanking Window

0 0 0 Blanking window off

0 0 1 0.5µs

010 1µs

0 1 1 1.5µs

100 2µs

1 0 1 2.5µs

110 3µs

1 1 1 3.5µs

ST7MC1xx/ST7MC2xx

216/309

MOTOR CONTROLLER (Cont’d)

MOTOR D EVENT FILTER REGISTER (MDFR)

Read/Write

Reset Value: 0000 1111 (0Fh)

Bits 7:4 = DEF[3:0]: D Event Filter bits

These bits select the number of valid consecutive

D events (when the D event is detected) needed to

generate the active event. Sampling is done at the

selected fSCF frequency, see Table 82.

Table 69. D Event filter Setting

Bit 3:0 = DWF[3:0]: D Window Filter bits

These bits select the length of the blanking win-

dow activated at each C event. The filter blanks

the D event detection.

Table 70. D Window Filter setting

Note: Times are indicated for 4 MHz fPERIPH

76543210

DEF3 DEF2 DEF1 DEF0 DWF3 DWF2 DWF1 DWF0

DEF3 DEF2 DEF1 DEF0 D event

Samples SR=1

0000 1

No D Event Filter

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

DWF3 DWF2 DWF1 DWF0

C to D

Window

Filter in

Sensorless

mode (SR=0)

SR=1

0000 5µs

No window filter after C event

0001 10µs

0010 15µs

0011 20µs

0100 25µs

0101 30µs

0110 35µs

0111 40µs

1000 60µs

1001 80µs

1010 100µs

1011 120µs

1100 140µs

1101 160µs

1110 180µs

1111 200µs

ST7MC1xx/ST7MC2xx

217/309

MOTOR CONTROLLER (Cont’d)

REFERENCE REGISTER (MREF)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = HST: Hysteresis Comparator Value.

This read only bit contains the hysteresis compa-

rator output.

0: Demagnetisation/BEMF comparator is under

VREF

1: Demagnetisation/BEMF comparator is above

VREF

Bit 6 = CL: Current Loop Comparator Value.

This read only bit contains the current loop compa-

rator output value.

0: Current detect voltage is under VCREF

1: Current detect voltage is above VCREF

Bit 5= CFAV: Current Feedback Amplifier entry

Validation

0: OAZ(MCCFI1) is the current comparator entry

1: MCCFI0 is the current comparator entry

Bits 4:3 = HFE[1:0]: Chopping mode selection

These bits select the chopping mode as shown in

the following table.

Table 71. Chopping mode

Bits 2:0 = HFRQ[2:0] : Chopper frequency selec-

tion

These bits select the chopping frequency.

Table 72. Chopping frequency selection

Note: The chopper signal has a 50% duty cycle.

76543 2 1 0

HST CL CFAV HFE1 HFE0 HFRQ2 HFRQ1 HFRQ0 HFE1 HFE0 Chopping mode

00 OFF

0 1 On Low channels only

1 0 On High channels only

1 1 Both High and Low channels

HFRQ2 HFRQ1 HFRQ0

Chopping

frequency

Fmtc = 16MHz

Fmtc = 8MHz

Chopping

frequency

Fmtc = 4MHz

0 0 0 100 KHz 50 KHz

0 0 1 200 KHz 100 KHz

0 1 0 400 KHz 200 KHz

0 1 1 500 KHz 250 KHz

1 0 0 800 KHz 400 KHz

1 0 1 1 MHz 500 KHz

1 1 0 1.33 MHz 666.66 MHz

1112 MHz 1 MHz

ST7MC1xx/ST7MC2xx

218/309

MOTOR CONTROLLER (Cont’d)

PWM CONTROL REGISTER (MPCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PMS: PWM Mode Selection.

0: Standard mode: bit b7 in the MCPxH register

represents the extension bit.

1: “8-bit” mode: bit b7 (extension bit) in the MCPxH

bits); the number of active bits in MCPxH and

MCPxL is decreased to b15:b8 instead of

b15:b3.

Bit 6 = OVFU: Phase U 100% duty cycle Selec-

tion.

0: Duty cycle defined by MCPUH:MCPUL register.

1: Duty cycle set at 100% on phase U at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 5 = OVFV: Phase V 100% duty cycle Selection.

0: Duty cycle defined by MCPVH:MCPVL register.

1: Duty cycle set at 100% on phase V at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 4 = OVFW: Phase W 100% duty cycle Selec-

tion.

0: Duty cycle defined by MCPWH:MCPWL regis-

ter.

1: Duty cycle set at 100% on phase W at next up-

date event and maintained till the next one. This

bit is reset once transferred to the active register

on update event.

Bit 3 = CMS: PWM Counter Mode Selection.

0: Edge-aligned mode

1: Center-aligned mode

Bits 2:0 = PCP[2:0] PWM counter prescaler value.

This value divides the Fmtc frequency by N, where

N is PCP[2:0] value. Table 73 shows the resulting

frequency of the PWM counter input clock.

Table 73. PWM clock prescaler

PMS OVFU OVFV OVFW CMS PCP2 PCP1 PCP0

PCP2 PCP1 PCP0 PWM counter input clock

000 Fmtc

001 Fmtc/2

010 Fmtc/3

011 Fmtc/4

100 Fmtc/5

101 Fmtc/6

110 Fmtc/7

111 Fmtc/8

ST7MC1xx/ST7MC2xx

219/309

MOTOR CONTROLLER (Cont’d)

REPETITION COUNTER REGISTER (MREP)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = REP[7:0] Repetition counter value (N).

This register allows the user to set-up the update

rate of the PWM counter compare register (i.e. pe-

riodic transfers from preload to active registers),

as well as the PWM Update interrupt generation

rate, if these interrupts are enabled.

Each time the MREP related Down-Counter

reaches zero, the Compare registers are updated,

a U interrupt is generated and it re-starts counting

from the MREP value.

After a microcontroller reset, setting the CKE bit in

the MCRA register (i.e. enabling the clock for the

MTC peripheral) forces the transfer from the

MREP preload register to its active register and

generates a U interrupt. During run-time (while

CKE bit = 1) a new value entered in the MREP

preload register is taken into account after a U

event.

As shown in Figure 122, (N+1) value corresponds

to:

– The number of PWM periods in edge-aligned

mode

– The number of half PWM periods in center-

aligned mode.

–

COMPARE PHASE W PRELOAD REGISTER

HIGH (MCPWH)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = CPWH[7:0] Most Significant Byte of

phase W preload value

COMPARE PHASE W PRELOAD REGISTER

LOW (MCPWL)

Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

Bits 7:5 = CPWL[7:3] Low bits of phase W preload

value.

Bits 2:0 = Reserved.

COMPARE PHASE V PRELOAD REGISTER

HIGH (MCPVH)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = CPVH[7:0] Most Significant Byte of

phase V preload value

COMPARE PHASE V PRELOAD REGISTER

LOW (MCPVL)

Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

Bits 7:5 = CPVL[7:3] Low bits of phase V preload

value.

Bits 2:0 = Reserved.

REP7 REP6 REP5 REP4 REP3 REP2 REP1 REP0

CPWH

CPWL

3---

CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0

CPVL7 CPVL6 CPVL5 CPVL4 CPVL3 - - -

ST7MC1xx/ST7MC2xx

220/309

MOTOR CONTROLLER (Cont’d)

COMPARE PHASE U PRELOAD REGISTER

HIGH (MCPUH)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = CPUH[7:0] Most Significant Byte of

phase U preload value

COMPARE PHASE U PRELOAD REGISTER

LOW (MCPUL)

Read/Write Read/Write (except bits 2:0)

Reset Value: 0000 0000 (00h)

Bits 7:5 = CPUL[7:3] Low bits of phase U preload

value.

Bits 2:0 = Reserved.

COMPARE 0 PRELOAD REGISTER HIGH

(MCP0H)

Read/Write (except bits 7:4)

Reset Value: 0000 1111 (0Fh)

Bits 7:4 = Reserved.

Bits 3:0 = CP0H[3:0] Most Significant Bits of Com-

pare 0 preload value.

COMPARE 0 PRELOAD REGISTER LOW

(MCP0L)

Read/Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CP0L[7:0] Low byte of Compare 0

preload value.

Note 1: The 16-bit Compare registers MCMPOx,

MCMPUx, MCMPVx, MCMPWx MSB and LSB

parts have to be written sequentially before being

taken into account when an update event occurs;

refer to section 10.6.10.4 on page 201 for details.

Note 2: The CPB, HDM, SDM, OS2 bits in the

MCRB and the bits OE[5:0] are marked with *. It

means that these bits are taken into account at the

following commutation event (in normal mode) or

when a value is written in the MPHST register

when in direct access mode. For more details, re-

fer to the description of the DAC bit in the MCRA

the registers to be updated at the same time.

Warning: Access to Preload registers

Special care has to be taken with Preload regis-

ters, especially when using the ST7 BSET and

BRES instructions on MTC registers.

For instance, while writing to the MPHST register,

you will write the value in the preload register.

However, while reading at the same address, you

will get the current value in the register and not the

value of the preload register.

Excepted for three-phase PWM generator’s regis-

ters, all preload registers are loaded in the active

registers at the same time. In normal mode this is

done automatically when a C event occurs, how-

ever in direct access mode (DAC bit=1) the

preload registers are loaded as soon as a value is

written in the MPHST register.

Caution: Access to write-once bits

Special care has to be taken with write-once bits in

MPOL and MDTG registers; these bits have to be

accessed first during the set-up. Any access to the

other bits (not write-once) through a BRES or a

BSET instruction will lock the content of write-once

bits (no possibility for the core do distinguish indi-

vidual bit access: Read/write internal signal acts

on a whole register only). This protection is then

only unlocked after a processor hardware reset.

CPUH

CPUL7 CPUL6 CPUL5 CPUL4 CPUL3 - - -

- - - - CP0H3 CP0H2 CP0H1 CP0H0

CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0

Comp‘ememaﬂ

ST7MC1xx/ST7MC2xx

221/309

MOTOR CONTROLLER (Cont’d)

DEAD TIME GENERATOR REGISTER (MDTG)

Read/Write (except bits 5:0 write once-only)

Reset Value: 1111 1111 (FFh)

Bit 7 = PCN: Number of PWM Channels .

0: Only PWM U signal is output to the PWM man-

ager for six-step mode motor control (e.g. PM

BLDC motors)

1: The three PWM signals U, V and W are output

to the channel manager (e.g. for three-phase

sinewave generation)

Bit 6 = DTE*: Dead Time Generator Enable

0: Disable the Dead Time generator

1: Enable the Dead Time generator and apply

complementary PWM signal to the adjacent

switch

* write once-only bit if PCN bit is set, read/write if

PCN bit is reset. To clear the DTE bit if PCN=1,

it is mandatory to clear the PCN bit first.

Table 74. DeadTime generator set-up

Note 1: This table is true on condition that the CKE

bit is set (Peripheral clock enabled) and the MOE

bit is set (MCOx outputs enabled). See Table 56,

“Output configuration summary,” on page 210

When the PCN bit is reset (e.g. for PM BLDC mo-

tors), in Direct Access mode (DAC=1), if the DTE

bit is reset, PWM signals can be applied on the

MCOx outputs but not complementary PWM. Of

course, logical levels can be also applied on the

outputs.

If the DTE bit is set (PCN=0 and DAC=1), chan-

nels are paired and complementary PWM signals

can be output on the MCOx pins. This will follow

the rules detailed in Table 53, “Dead Time genera-

tor outputs,” on page 197 as the channels are

grouped in pairs.

In this case, the PWM application is selected by

the OS0 bit in the MCRB register.

It is also possible to add a chopper on the PWM

signal output using bits HFE[1:0] and HFRQ[2:0] in

the MREF register.

Caution 1: The PWM mode will be selected via

the 00[5:0] bits in the MPHST register, the OE[5:0]

bits in the MPAR register and the OS2 and OS0

bits in the MCRB register as shown in Table 62,

“PWM mode when SR=1,” on page 213.

Caution 2: When driving motors with three inde-

pendent pairs of complementary PWM signals

(PCN=1), disabling the deadtime generator

(DTE=0) causes the deadtime to be null: high and

low side signals are exactly complemented.

It is therefore recommended not to disable the

deadtime generator (it may damage the power

stage), unless deadtimes are inserted externally.

Bits 5:0 = DTG[5:0]* Dead time generator set-up.

These bits set-up the deadtime duration and reso-

lution. Refer to Table 52, “Dead time programming

and example,” on page 195 for details.

With Fmtc = 16MHz dead time values range from

125ns to 16µs with steps of 125ns, 250ns and

500ns.

* Write-once bits; once write-accessed these bits

cannot be re-written unless the processor is reset

(See “Caution: Access to write-once bits” on

page 220.).

PCN DTE DTG5 DTG4 DTG3 DTG2 DTG1 DTG0

DAC

PCN bit

in MDTG

DTE bit

in MDTG

Complementary PWM

applied to adjacent

switch

00 0 NO

00 1 YES

01 1 YES

01 0 YES, but

WITHOUT deadtime

10 0

NO Complementary

PWM

10 1 YES

11 1 YES

11 0 YES, but

WITHOUT deadtime

ST7MC1xx/ST7MC2xx

222/309

MOTOR CONTROLLER (Cont’d)

POLARITY REGISTER (MPOL)

Read/Write (some bits write-once)

Reset Value: 0011 1111 (3Fh)

Bit 7 = ZVD: Z vs D edge polarity.

0: Zero-crossing and End of Demagnetisation

have opposite edges

1: Zero-crossing and End of Demagnetisation

have same edge

Bit 6 = REO: Read on High or Low channel bit

0: Read the BEMF signal on High channels

1: Read on Low channels

Note: This bit always has to be configured whatev-

er the sampling method.

Bits 5:0 = OP[5:0]*: Output channel polarity.

These bits are used together with the OO[5:0] bits

in the MPHST register to control the output chan-

nels.

0: Output channel is Active Low

1: Output channel is Active High.

* Write-once bits; once write-accessed these bits

cannot be re-written unless the processor is reset

(See “Caution: Access to write-once bits” on

page 220.).

Table 75. Output Channel State Control

Warning: OP[5:0] bits in the MPOL register must

be configured as required by the application be-

fore enabling the MCO[5:0] outputs with the MOE

bit in the MCRA register.

76543210

ZVD REO OP5 OP4 OP3 OP2 OP1 OP0

OP[5:0] bit OO[5:0] bit MCO[5:0] pin

00 1 (Off)

0 1 0 (PWM possible)

10 0 (Off)

1 1 1 (PWM possible)

ST7MC1xx/ST7MC2xx

223/309

MOTOR CONTROLLER (Cont’d)

PWM REGISTER (MPWME)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = DG:Debug Option.

This bit is used to enter debug mode. As a result,

C, D and Z events are output on 2 pins MCDEM

and MCZEM in Switched and Autoswitched mode,

C and U events are output in Speed Measurement

mode. Refer to section10.6.7.3 on page 172 for

more details

0: Normal mode

1: Debug mode

Bit 6 = PWMW: PWM W output control

0: PWM on Compare Register W is not output on

MCPWMW pin

1: PWM on Compare Register W is output on

MCPWMW pin

Bit 5 = PWMV: PWM V output control

0: PWM on Compare Register V is not output on

MCPWMV pin

1: PWM on Compare Register V is output on MCP-

WMV pin

Bit 4 = PWMU: PWM U output control

0: PWM on Compare Register U is not output on

MCPWMU pin

1: PWM on Compare Register U is output on

MCPWMU pin

Bits 3:0 = OT[3:0]: Off Time selection

These bits are used to select the OFF time in sen-

sorless current mode as shown in the following ta-

ble.

Table 76. OFF time bits

Note: Times are indicated for 4 MHz fPERIPH

76543210

DG PWMW PWMV PWMU OT3 OT2 OT1 OT0

OT3OT2OT1OT0

Off Time sen-

sorless mode

(SR=0)

(DS[3:0]=0)

Sensor Mode

(SR=1) or sam-

pling during ON

ime in sensor-

less (SPLG =1

and/or DS [3:0]

bits)

0000 2.5 µs

No minimum off -

time

0001 5 µs

0010 7.5 µs

0 0 1 1 10 µs

0 1 0 0 12.5 µs

0 1 0 1 15 µs

0 1 1 0 17.5 µs

0 1 1 1 20 µs

1 0 0 0 22.5 µs

1 0 0 1 25 µs

1 0 1 0 27.5 µs

1 0 1 1 30 µs

1 1 0 0 32.5 μs

1101 35 μs

1 1 1 0 37.5 μs

1111 40 μs

XT16 XT8 Peripheral frequency PER‘PH fMTC PER‘PH fMTC PER‘PH fMTC

ST7MC1xx/ST7MC2xx

224/309

MOTOR CONTROLLER (Cont’d)

CONFIGURATION REGISTER (MCONF)

Read/Write

Reset Value: 0000 0010 (02h)

Bits 7:4 = DS[3:0]: Delay for sampling at Ton

These bits are used to define the delay inserted

before sampling in order to sample during PWM

ON time.

Table 77. Sampling Delay

Note: Times are indicated for 4 MHz fPERIPH

Bit 3 = SOI Sampling Out Interrupt flag.

This interrupt indicates that the sampling that

should have been done during Ton has occured

during the next Toff. In this case, the sample is dis-

carded.

0: No Sampling Out Interrupt Pending

1: Sampling Out Interrupt Pending

Bit 2 = SOM: Sampling Out Mask bit.

This interrupt is available only for Z event sampling

as D event sampling is always done at fSCF high

frequency.

0: Sampling Out interrupt disabled

1: Sampling Out interrupt enabled

This interrupt is available only when a delay has

been set in the DS[3:0] bits in the MCONF register.

Note: It is recommended to disable the sampling

out interrupt when software Z event is enabled (SZ

bit in MCRC register is set) and if the value in the

DS[3:0] bits is modified to change the sampling

method during the application.

Bits [1:0] = XT16:XT8 BLDC drive Motor Control

Peripheral input frequency selection:

Table 78. Peripheral frequency

Caution: It is recommended to set the peripheral

frequency to 4MHz. Setting fPERIPH=fMTC is used

mainly when fclk = 4MHz (for low power consump-

tion).

76543210

DS3 DS2 DS1 DS0 SOI SOM XT16 XT8

DS3 DS2 DS1 DS0 Delay added to sample at Ton

0 0 0 0 No delay added. Sample during Toff

0 0 0 1 2.5 µs

0 0 1 0 5 µs

0 0 1 1 7.5 µs

0 1 0 0 10 µs

0 1 0 1 12.5 µs

0 1 1 0 15 µs

0 1 1 1 17.5 µs

1 0 0 0 20 µs

1 0 0 1 22.5 µs

1 0 1 0 25 µs

1 0 1 1 27.5 µs

1100 30

μs

1 1 0 1 32.5 μs

1110 35 μs

1 1 1 1 37.5 μs

XT16 XT8 Peripheral frequency

00fPERIPH=fMTC

01fPERIPH=fMTC/2

fPERIPH=fMTC/4

(same as XT16=1,XT8=0)

ST7MC1xx/ST7MC2xx

225/309

MOTOR CONTROLLER (Cont’d)

PARITY REGISTER (MPAR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:6 = TES[1:0] : Tacho Edge Selection bits

The primary function of these bits is to select the

edge sensitivity of the tachogenerator capture log-

ic; clearing both TES[1:0] bits specifies that the In-

put Detection block does not operate in Speed

Sensor Mode but either in Position Sensor or Sen-

sorless Mode for a six-step motor drive).

Table 79. Tacho edges and input mode selection

Bits 5:0 = OE[5:0]: Output Parity Mode.

0: Output channel is High

1: Output channel Low

Note: These bits are not significant when PCN=1

(configuration with three independent phases).

76543210

TES1 TES0 OE5 OE4 OE3 OE2 OE1 OE0

TES 1 TES 0 Edge sensitivity Operating Mode

0 0 Not applicable Position Sensor or

Sensorless

0 1 Rising edge Speed Sensor

1 0 Falling edge Speed Sensor

Rising and falling

edges Speed Sensor

ST7MC1xx/ST7MC2xx

226/309

MOTOR CONTROLLER (Cont’d)

MOTOR Z EVENT FILTER REGISTER (MZFR)

Read/Write

Reset Value: 0000 1111 (0Fh)

Bits 7:4 = ZEF[3:0]: Z Event Filter bits

These bits select the number of valid consecutive

Z events (when the Z event is detected) needed to

generate the active event. Sampling is done at the

selected fSCF frequency (see Table 82.) or at

PWM frequency.

Table 80. Z Event filter Setting

Bits 3:0 = ZWF[3:0]: Z Window Filter bits

These bits select the length of the blanking win-

dow activated at each D event. The filter blanks

the Z event detection until the end of the time win-

dow.

Table 81. Z Window filter Setting

Note: Times are indicated for 4 MHz fPERIPH

76543210

ZEF3 ZEF2 ZEF1 ZEF0 ZWF3 ZWF2 ZWF1 ZWF0

ZEF3 ZEF2 ZEF1 ZEF0 Z event Samples

0000 1

0001 2

0010 3

0011 4

0100 5

0101 6

0110 7

0111 8

1000 9

1001 10

1010 11

1011 12

1100 13

1101 14

1110 15

1111 16

ZWF3 ZWF2 ZWF1 ZWF0

D to Z window fil-

ter in Sensorless

Mode (SR=0)

SR=1

0000 5 µs

Win-

dow

Filter

after

event

0001 10 µs

0010 15 µs

0011 20 µs

0100 25 µs

0101 30 µs

0110 35 µs

0111 40 µs

1000 60 µs

1001 80 µs

1010 100 µs

1011 120 µs

1100 140 µs

1101 160 µs

1110 180 µs

1111 200 µs

ST7MC1xx/ST7MC2xx

227/309

MOTOR CONTROLLER (Cont’d)

MOTOR SAMPLING CLOCK REGISTER

(MSCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = ZSV Z Event Sampling Validation when

MOE bit is reset

This bit enables/disables Z event sampling in ei-

ther mode (sampling at PWM frequency or at fSCF

frequency selected by SCF[1:0] bits)

0: Z event sampling disabled

1: Z event sampling enabled

Bits 6:4 = Reserved, must be kept cleared.

Bits 3:2 = SCF[1:0] Sampling Clock Frequency

These bits select the sampling clock frequency

(fSCF) used to count D & Z events.

Table 82. Sampling Clock Frequency

Note: Times are indicated for 4 MHz fPERIPH

Bit 1 = ECM: Encoder Capture Mode

This bit is used to select the source of events

which trigger the capture of the [MTIM:MTIML]

counter when using Encoder speed sensor (see

Figure 90).

0: Real-time Clock interrupts

1: Read access on MTIM register

Bit 0 = DISS Data Input Selection

This setting is effective only if PCN=0, TES=00

and SR=0.

0: Unused MCIx inputs are grounded

1: Unused MCIx inputs are put in HiZ

76543210

ZSV 0 0 0 SCF1 SCF0 ECM DISS

SCF1 SCF0 fSCF

0 0 1 MHz (every 1µs)

0 1 500 kHz (every 2µs)

1 0 250 kHz (every 4µs)

1 1 125 kHz (every 8µs)

ST7MC1xx/ST7MC2xx

228/309

MOTOR CONTROLLER (Cont’d)

Figure 123. General view of the MTC for PM BLDC motor control

MTIM [8-bit Up Counter]

Microcontroller

REF

MPOL Reg

MOE bit

MCCFI0

MCO0

MCO2

MCO4

MCO1

MCO3

MCO5

bit

Board + Motor

CFF[2:0] bit

VR2-0

MCIC

MCIA

MCIB

MWGHT Reg [a

n+1

]

MZREG Reg [Z

]

A x B / 256

Fmtc

MZPRV Reg [Z

n-1

]

S,H

ST3-0 bits 4

DCB bit SDM

bit

SWA bit

MDREG Reg [D

]

Compare

MCOMP Reg [C

n+1

]

1 / 2

Ratio

1 / 2

MZREG

MTIM

S,H

SA3-0 &

12-bit PWM generator

NMCES

-1

clr

x6 x6

MISR Reg

S,H

MPAR Reg

➘

1/128

OT1-0 bits

nn-1

-/+

MIMR Reg

MPHST

Reg

SR bit

ext

S,H

1 /20

1 / 4

S,H

< 55h?

= FFh?

Filter / C

SWA bit

(V)

R1ext

R2ext

VDD

(I)

Compare U

MCPWMU

MCPWMV

MCPWMW

MCVREF

SPLG

DWF[3:0]

Compare

Filter / D

ZWF[3:0]

bit

Ch0

Ch1

Ch2

Ch3Ch4

Ch5 bits

PCN bit =0

MDTG register

Dead

Time

Dead

Time

Dead

Time

High Frequency Chopper

OAP

OAN

MCCREF

MCPWMU/V/W

OAON

MPWME Reg

MREF

Reg

CLI

XT16:XT8 bit

OAZ(MCCFI1)

CFAV bit

drivers

CLIM bit

CLI bit

OCV bit

Fperiph

PRESCALER

D/Z Window filter

Z event generation

D event generation

CFW[2:0] bit

?????? E]

ST7MC1xx/ST7MC2xx

229/309

MOTOR CONTROLLER (Cont’d)

Figure 124. General view of the MTC configured for Induction motor control (proposal)

Microcontroller

MPOL Reg

MOE bit

MCCFI0

MCO0

MCO2

MCO4

MCO1

MCO3

MCO5

bit

Board + Motor

MCIC

MCIA

MCIB

Fmtc

NMCES

x6 x6

MISR Reg

MPAR Reg

6 1

-/+

MIMR Reg

PCN bit =1

MDTG register

Dead

Time

Dead

Time

Dead

Time

High Frequency Chopper

OAP

OAN

MCCREF

OAON

MREF

Reg

OAZ (MCCFI1)

CFAV bit

Compare

Clock

MSbits

clr

MTIM MTIML

MZREG MZPRV

LSbits

MDREG

up to 16MHz

ST[3:0] Bits 4

1 / 2

Ratio

MZREG < 55h?

MTIM = FFh?

-1

IS[1:0] bits

TES[1:0] bits

IS[1:0] bits TES[1:0] bitsECM bit

MTIM Read

RTC interrupt

Compare

FFh (Fixed)

Encoder Clock Encoder

interface

Direction

oror

EDIR bit

Tacho

Capture

TES bits

Clock Ratio

MCIA

MCIB

MCIA

or MCIB

or MCIC

Tachogenerator

Incremental Encoder

Three-phase

Induction motor

12-bit Compare 0 Register

12-bit PWM Counter

13-bit Compare W Register

Up to 16MHz

Phase W

13-bit Compare U Register Phase U

13-bit Compare V Register

Phase V

Clear or

PCP[2:0] bits

Repetition Counter

MPCR Register

Up/Down

MREP Reg

PWM Clock

Fmtc

drivers

16-bit Capture register

16-bit Up Counter

CLIM bit

CLI bit

OCV bit

ST7MC1xx/ST7MC2xx

230/309

MOTOR CONTROLLER (Cont’d)

Table 83. MTC Page 0 Register Map and Reset Values

MTIM

Reset Value

MTIML

Reset Value

TL7

TL6

TL5

TL4

TL3

TL2

TL1

TL0

MZPRV

Reset Value

ZP7

ZP6

ZP5

ZP4

ZP3

ZP2

ZP1

ZP0

MZREG

Reset Value

ZC7

ZC6

ZC5

ZC4

ZC3

ZC2

ZC1

ZC0

MCOMP

Reset Value

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

MDREG

Reset Value

DN7

DN6

DN5

DN4

DN3

DN2

DN1

DN0

MWGHT

Reset Value

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

MPRSR

Reset Value

SA3

SA2

SA1

SA0

ST3

ST2

ST1

ST0

MIMR

Reset Value

PUM

SEM

RIM

CLIM

EIM

ZIM

DIM

CIM

MISR

Reset Value

PUI

RPI

RMI

CLI

MCRA

Reset Value

MOE

CKE

DAC

V0C1

SWA

DCB

MCRB

Reset Value 0CPB

HDM

SDM

OCV

OS2

OS1

OS0

MCRC

Reset Value

SEI / OI

EDIR / HZ

SPLG

VR2

VR1

VR0

MPHST

Reset Value

IS1

IS0

OO5

OO4

OO3

OO2

OO1

OO0

MDFR

Reset Value

DEF3

DEF2

DEF1

DEF0

DWF3

DWF2

DWF1

DWF0

MCFR

Reset Value

RPGS

RST

CFF2

CFF1

CFF0

CFW2

CFW1

CFW0

MREF

Reset Value

HST

CFAV

HFE1

HFE0

HFRQ2

HFRQ1

HFRQ0

MPCR

Reset Value

PMS

OVFU

OVFV

OVFW

CMS

PCP2

PCP1

PCP0

MREP

Reset Value

REP7

REP6

REP5

REP4

REP3

REP2

REP1

REP0

MCPWH

Reset Value

CPWH7

CPWH6

CPWH5

CPWH4

CPWH3

CPWH2

CPWH1

CPWH0

ST7MC1xx/ST7MC2xx

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Table 84. MTC Page 1 Register Map and Reset Values

MCPWL

Reset Value

CPWL7

CPWL6

CPWL5

CPWL4

CPWL3

0000

MCPVH

Reset Value

CPVH7

CPVH6

CPVH5

CPVH4

CPVH3

CPVH2

CPVH1

CPVH0

MCPVL

Reset Value

CPVL7

CPVL6

CPVL5

CPVL4

CPVL3

0000

MCPUH

Reset Value

CPUH7

CPUH6

CPUH5

CPUH4

CPUH3

CPUH2

CPUH1

CPUH0

MCPUL

Reset Value

CPUL7

CPUL6

CPUL5

CPUL4

CPUL3

0000

MCP0H

Reset Value 0000

CP0H3

CP0H2

CP0H1

CP0H0

MCP0L

Reset Value

CP0L7

CP0L6

CP0L5

CP0L4

CP0L3

CP0L2

CP0L1

CP0L0

MDTG

Reset Value

PCN

DTE

DTG5

DTG4

DTG3

DTG2

DTG1

DTG0

MPOL

Reset Value

ZVD

REO

OP5

OP4

OP3

OP2

OP1

OP0

MPWME

Reset Value

PWMW

PWMV

PWMU

OT3

OT2

OT1

OT0

MCONF

Reset Value

DS3

DS2

DS1

DS0

SOI

SOM

XT16

XT8

MPAR

Reset Value

TES1

TES0

OE5

OE4

OE3

OE2

OE1

OE0

MZFR

Reset Value

ZEF3

ZEF2

ZEF1

ZEF0

ZWF3

ZWF2

ZWF1

ZWF0

MSCR

Reset Value

ZSV

0000

SCF1

SCF0

ECM

DISS

ST7MC1xx/ST7MC2xx

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MOTOR CONTROLLER (Cont’d)

Figure 125. Page Mapping for Motor Control

10.6.14 Related Documentation

AN1904: ST7MC Three-phase AC Induction Motor

Control Software Library

AN1905: ST7MC Three-Phase BLDC Motor Con-

trol Software Library

AN1946: Sensorless BLDC Motor Control And

BEMF Sampling Methods With ST7MC

AN1947: ST7MC PMAC Sine Wave Motor Control

Software Library

AN2009: PWM Management For 3-phase BLDC

Motor Drives Using The ST7FMC

AN2030: Back EMF Detection During PWM On

Time By ST7MC

PAGE 0

MTIM

MTIML

MDFR

MCFR

MZPRV

MZREG

MCOMP

MDREG

MWGHT

MPRSR

MIMR

MISR

MCRA

MCRB

MCRC

MPHST

MREF

MPCR

MREP

MCPUH

MCPUL

MCPWH

MCPWL

MCPVH

MCPVL

MCPOH

MCPOL

PAGE 1

MDTG

MPOL

MCONF

MPAR

RPGS bit =1 in MCFR register

MPWME

MZFR

MSCR

ST7MC1xx/ST7MC2xx

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10.7 OPERATIONAL AMPLIFIER (OA)

10.7.1 Introduction

The ST7 Op-Amp module is designed to cover

various types of microcontroller applications

where analog signals amplifiers are used.

It may be used to perform a variety of functions

such as: differential voltage amplifier, comparator/

threshold detector, ADC zooming, impedance

adaptor, general purpose operational amplifier.

10.7.2 Main Features

This module includes:

■1 stand alone Op-Amp that may be externally

connected using I/O pins

■Op-Amp output can be internally connected to

the ADC inputs as well as to the motor control

current feedback comparator input

■Input offset compensation with optional average

■On/Off bit to reduce power consumption and to

enable the input/output connections with

external pins

10.7.3 General Description

This Op-Amp can be used with 3 external pins

(see device pinout description) and can be inter-

nally connected to the ADC and the Motor Control

cells. The gain must be fixed with external compo-

nents.

The input/output pins are connected to the Op-

Amp as soon as it is switched ON (through the

OACSR register).

The analog input ports must be configured as in-

put, no pull-up, no interrupt. Refer to the “I/O ports”

chapter. Using these pins as analog inputs does

not affect the ability of the port to be read as a logic

input.

The output is not connected (HiZ) when the Op-

Amp is OFF. However the pin can still be used as

an ADC or MTC input in this case.

When the Op-Amp is ON the output is connected

to a dedicated pin which is not a standard I/O port.

The output can be also be connected to the ADC

or the MTC. The switches are controlled software

(refer to the MTC and ADC chapters).

10.7.4 Input Offset Compensation

The Op-Amp incorporates a method to minimize

the input offset which is dependant on process lot.

It is useable by setting the OFFCMP bit of the con-

trol register, which launch the compensation cycle.

The CMPVR bit is set by hardware as soon as this

cycle is completed. The compensation is valid as

long as the OFFCMP bit is high. It can be re-per-

formed by cycling OFFCMP ‘0’ then ‘1’.

The compensation can be improved by averaging

the calculation (over 16 times) setting the AVGC-

MP bit.

Compensamon Offset 7

ST7MC1xx/ST7MC2xx

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OP-AMP MODULE (Cont’d)

10.7.5 Op-Amp Programming

The flowchart for Op-Amp operation is shown in

Figure 126

Figure 126. Normal Op-Amp Operation

Power On Reset

OACSR = 0000 0000

Write OACSR = x0010xx0

Wait for Amplifier to wake up (Twakeup)

Compensation Offset ?

Average Compensation ?

Write OACSR = x101 0xx0

Wait for 1536*TCPU cycles

Read CMPOVR = 1

Write OACSR = x0p1 pxx0

p : same as before

Write OACSR = x111 0xx0

Wait for 24576*TCPU cycles

Read CMPOVR = 1

Need

closed loop gain > 20dB @ 100kHz ?

Write OACSR = x1p1 1xx0

p : same as before

Op-Amp useable

Re-compensate

Offset ?

External components always connected

Yes

Yes No

Yes

#OFFCMP & AVGCMP

should be set simultenaously

#The HIGHGAIN bit can also be written in step (1) or (2)

(1)

(2b)

(4)

(3) #

(2a)

ST7MC1xx/ST7MC2xx

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OP-AMP MODULE (Cont’d)

10.7.6 Low power modes

Note: The Op-Amp can be disabled by resetting

the OAON bit. This feature allows reduced power

consumption when the amplifier is not used.

10.7.7 Interrupts

None.

10.7.8 Register Description

CONTROL/STATUS REGISTER (OACSR)

Read/Write (except bit 7 read only)

Reset Value: 0000 0000(00h)

Bit 7 = CMPOVR Compensation Completed

This read-only bit contains the offset compensa-

tion status.

0: No offset compensation if OFFCMP = 0, or

Offset compensation cycle not completed if

OFFCMP = 1

1: Offset compensation completed if OFFCMP = 1

Bit 6 = OFFCMP Offset Compensation

0: Reset offset compensation values

1: Request to start offset compensation

Bit 5 = AVGCMP Average Compensation

0: One-shot offset compensation

1: Average offset compensation over 16 times

Bit 4 = OAON Amplifier On

0: Op-Amp powered off

1: Op-Amp on

Bit 3 = HIGHGAIN Gain range selection

This bit must be programmed depending on the

application. It can be used to ensure 35dB open

loop gain when high, it must be low when the

closed loop gain is below 20dB for stability rea-

sons.

0: Closed loop gain up to 20dB

1: Closed loop gain more than 20dB

Bits 2:0 = Reserved, must be kept cleared.

Mode Description

Wait No effect on Op-Amp

Halt

Op-Amp disabled

After wake-up from Halt mode, the Op-

Amp requires a stabilization time (see

Electrical characteristics) (to be defined)

76543210

CMP

OVR OFF

CMP AVG

CMP

OAO

HIGH

GAIN

000

:1 \—

ST7MC1xx/ST7MC2xx

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10.8 10-BIT A/D CONVERTER (ADC)

10.8.1 Introduction

The on-chip Analog to Digital Converter (ADC) pe-

ripheral is a 10-bit, successive approximation con-

verter with internal sample and hold circuitry. This

peripheral has up to 16 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 16 different sources.

The result of the conversion is stored in 2 8-bit

Data Registers. The A/D converter is controlled

through a Control/Status Register.

10.8.2 Main Features

■10-bit conversion

■Up to 16 channels with multiplexed input

■2 software-selectable sample times

■External positive reference voltage VREF+ can

be independent from supply

■Linear successive approximation

■Data registers (DR) which contain the results

■Conversion complete status flag

■Maskable interrupt

■On/off bit (to reduce consumption)

The block diagram is shown in Figure 127.

10.8.3 Functional Description

10.8.3.1 Analog References

VREF+ and VREF- are the high and low level refer-

ence voltage pins. Conversion accuracy may

therefore be impacted by voltage drops and noise

on these lines. VREF+ can be supplied by an inter-

mediate supply between VDDA and VSSA to

change the conversion voltage range. VREF- must

be tied to VSSA. An internal resistor bridge is im-

plemented between VREF+ and VREF- pins, with a

typical value of 15kΩ

10.8.3.2 Analog Power Supply

VDDA and VSSA are the supply and ground pins

providing power to the converter part. They must

be tied to VDD and VSS respectively.

Figure 127. ADC Block Diagram

CS2 CS1EOC PRSC1PRSC0 ADON CS0 ADCCSR

AIN0

AIN1 ANALOG TO DIGITAL

CONVERTER

AINx

ANALOG

MUX

D4 D3D5D9 D8 D7 D6 D2

ADCDRMSB

fADC

D1 D0

ADCDRLSB

PRESCALER

00 00 00

CS3

MCCBCR

request

ADCIE

ADSTS

ST7MC1xx/ST7MC2xx

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.3.3 Digital A/D Conversion Result

The conversion is monotonic, meaning that the re-

sult never decreases if the analog input does not

and never increases if the analog input does not.

If the input voltage (VAIN) is greater than VREF+

(high-level voltage reference) then the conversion

result is FFh in the ADCDRMSB register and 03h

in the ADCDRLSB register (without overflow indi-

cation).

If the input voltage (VAIN) is lower than VREF- (low-

level voltage reference) then the conversion result

in the ADCDRMSB and ADCDRLSB registers is

00 00h.

The A/D converter is linear and the digital result of

the conversion is stored in the ADCDRMSB and

ADCDRLSB registers. The accuracy of the con-

version is described in the Electrical Characteris-

tics Section.

RAIN is the maximum recommended impedance

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

RREF is the value of the resistive bridge imple-

mented in the device between VREF+ and VREF-.

10.8.3.4 A/D Conversion

The analog input ports must be configured as in-

put, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input. If the application used the high-im-

pedance analog inputs, then the sample time

should be stretched by setting the ADSTS bit in

the MCCBCR register.

In the ADCCSR register:

– Select the CS[3:0] bits to assign the analog

channel to convert.

ADC Conversion mode

In the ADCCSR register:

– Set the ADON bit to enable the A/D converter

and to start the conversion. From this time on,

the ADC performs a continuous conversion of

the selected channel.

– The EOC bit is kept low by hardware during the

conversion.

Note: Changing the A/D channel during conver-

sion will stop the current conversion and start con-

version of the newly selected channel.

ST7MC1xx/ST7MC2xx

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10-BIT A/D CONVERTER (ADC) (Cont’d)

When a conversion is complete:

– The EOC bit is set by hardware

– An interrupt request is generated if the ADCIE

bit in the MCCBCR register is set (see section

6.4.7 on page 38).

– The result is in the ADCDR registers and re-

mains valid until the next conversion has end-

ed.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit or wait for EOC interrupt

2. Read ADCDRLSB

3. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit or wait for EOC interrupt

2. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

Changing the conversion channel

The application can change channels during con-

version. In this case the current conversion is

stopped and the A/D converter starts converting

the newly selected channel.

ADCCR consistency

If an End Of Conversion event occurs after soft-

ware has read the ADCDRLSB but before it has

read the ADCDRMSB, there would be a risk that

the two values read would belong to different sam-

ples.

To guarantee consistency:

– The ADCDRMSB and the ADCDRLSB are

locked when the ADCCRLSB is read

– The ADCDRMSB and the ADCDRLSB are un-

locked when the MSB is read or when ADON

is reset.

Thus, it is mandatory to read the ADCDRMSB just

after reading the ADCDRLSB. Otherwise the AD-

CDR register will not be updated until the AD-

CDRMSB is read.

10.8.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed.

10.8.5 Interrupts

1)The ADCIE bit is in the MCCBCR register (see

section 6.4.7 on page 38)

Mode Description

Wait No effect on A/D Converter

Halt

A/D Converter disabled.

After wake up from Halt mode, the A/D

Converter requires a stabilization time

tSTAB (see Electrical Characteristics)

before accurate conversions can be

performed.

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

End of Conver-

sion EOC ADCIE1) Yes No

ST7MC1xx/ST7MC2xx

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by soft-

ware reading the ADCDRMSB register.

0: Conversion is not complete

1: Conversion complete

Bit 6:5 = PRSC[1:0] ADC clock prescaler selection

These bits are set and cleared by software.

Bit 4 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 3:0 = CS[3:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

*The number of channels is device dependent. Refer to

the device pinout description.

DATA REGISTER (ADCDRMSB)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[9:2] MSB of Analog Converted Value

This register contains the MSB of the converted

analog value.

DATA REGISTER (ADCDRLSB)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Analog Converted Value

This register contains the LSB of the converted an-

alog value.

EOC PRSC1 PRSC0 ADON CS3 CS2 CS1 CS0

fADC PRSC1 PRSC0

4MHz 0 0

2MHz 0 1

1MHz 1 0

Channel Pin* CH3 CH2 CH1 CH0

AIN0 0000

AIN1 0001

AIN2 0010

AIN3 0011

AIN4 0100

AIN5 0101

AIN6 0110

AIN7 0111

AIN8 1000

AIN9 1001

AIN10 1010

AIN11 1011

AIN12 1100

AIN13 1101

AIN14 1110

AIN15 1111

D9 D8 D7 D6 D5 D4 D3 D2

000000D1D0

ST7MC1xx/ST7MC2xx

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10-BIT A/D CONVERTER (ADC) (Cont’d)

Table 85. ADC Register Map and Reset Values

Address

(Hex.)

Label 76543210

2E ADCCSR

Reset Value

EOC

PRSC1

PRSC0

ADON

CS3

CS2

CS1

CS0

2F ADCDRMSB

Reset Value

30 ADCDRLSB

Reset Value

ST7MC1xx/ST7MC2xx

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11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES

The CPU features 17 different addressing modes

which can be classified in 7 main groups:

The CPU Instruction set is designed to minimize

the number of bytes required per instruction: To do

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and

short addressing modes.

Table 86. CPU Addressing Mode Overview

Addressing Mode Example

Inherent nop

Immediate ld A,#$55

Direct ld A,$55

Indexed ld A,($55,X)

Indirect ld A,([$55],X)

Relative jrne loop

Bit operation bset byte,#5

Mode Syntax Destination

Pointer

Address

(Hex.)

Pointer Size

(Hex.)

Length

(Bytes)

Inherent nop + 0

Immediate ld A,#$55 + 1

Short Direct ld A,$10 00..FF + 1

Long Direct ld A,$1000 0000..FFFF + 2

No Offset Direct Indexed ld A,(X) 00..FF + 0

Short Direct Indexed ld A,($10,X) 00..1FE + 1

Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2

Short Indirect ld A,[$10] 00..FF 00..FF byte + 2

Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2

Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2

Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2

Relative Direct jrne loop PC+/-127 + 1

Relative Indirect jrne [$10] PC+/-127 00..FF byte + 2

Bit Direct bset $10,#7 00..FF + 1

Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2

Bit Direct Relative btjt $10,#7,skip 00..FF + 2

Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3

ST7MC1xx/ST7MC2xx

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

11.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

11.1.3 Direct

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Direct (short)

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three

sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

Inherent Instruction Function

NOP No operation

TRAP S/W Interrupt

WFI Wait For Interrupt (Low Pow-

er Mode)

HALT Halt Oscillator (Lowest Power

Mode)

RET Sub-routine Return

IRET Interrupt Sub-routine Return

SIM Set Interrupt Mask (level 3)

RIM Reset Interrupt Mask (level 0)

SCF Set Carry Flag

RCF Reset Carry Flag

RSP Reset Stack Pointer

LD Load

CLR Clear

PUSH/POP Push/Pop to/from the stack

INC/DEC Increment/Decrement

TNZ Test Negative or Zero

CPL, NEG 1 or 2 Complement

MUL Byte Multiplication

SLL, SRL, SRA, RLC,

RRC Shift and Rotate Operations

SWAP Swap Nibbles

Immediate Instruction Function

LD Load

CP Compare

BCP Bit Compare

AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC Arithmetic Operations

ST7MC1xx/ST7MC2xx

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

The indirect indexed addressing mode consists of

two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

Table 87. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

11.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC

it.

The relative addressing mode consists of two sub-

modes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

The offset is defined in memory, which address

follows the opcode.

Long and Short

Instructions Function

LD Load

CP Compare

AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC Arithmetic Additions/Sub-

stractions operations

BCP Bit Compare

Short Instructions

Only Function

CLR Clear

INC, DEC Increment/Decrement

TNZ Test Negative or Zero

CPL, NEG 1 or 2 Complement

BSET, BRES Bit Operations

BTJT, BTJF Bit Test and Jump Opera-

tions

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Opera-

tions

SWAP Swap Nibbles

CALL, JP Call or Jump subroutine

Available Relative

Direct/Indirect

Instructions

Function

JRxx Conditional Jump

CALLR Call Relative

ST7MC1xx/ST7MC2xx

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in

the following table:

Using a pre-byte

The instructions are described with one to four op-

codes.

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PC opcode

PC+1 Additional word (0 to 2) according

to the number of bytes required to compute the ef-

fective address

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

PDY 90 Replace an X based instruction

using immediate, direct, indexed, or inherent ad-

dressing mode by a Y one.

PIX 92 Replace an instruction using di-

rect, direct bit, or direct relative addressing mode

to an instruction using the corresponding indirect

addressing mode.

It also changes an instruction using X indexed ad-

dressing mode to an instruction using indirect X in-

dexed addressing mode.

PIY 91 Replace an instruction using X in-

direct indexed addressing mode by a Y one.

11.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de-

vice against unexpected behaviour, a system of il-

legal opcode detection is implemented. If a code to

be executed does not correspond to any opcode

or prebyte value, a reset is generated. This, com-

bined with the Watchdog, allows the detection and

recovery from an unexpected fault or interference.

Note: A valid prebyte associated with a valid op-

code forming an unauthorized combination does

not generate a reset.

Load and Transfer LD CLR

Stack operation PUSH POP RSP

Increment/Decrement INC DEC

Compare and Tests CP TNZ BCP

Logical operations AND OR XOR CPL NEG

Bit Operation BSET BRES

Conditional Bit Test and Branch BTJT BTJF

Arithmetic operations ADC ADD SUB SBC MUL

Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA

Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET

Conditional Branch JRxx

Interruption management TRAP WFI HALT IRET

Condition Code Flag modification SIM RIM SCF RCF

ST7MC1xx/ST7MC2xx

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

ADC Add with Carry A = A + M + C A M H N Z C

ADD Addition A = A + M A M H N Z C

AND Logical And A = A . M A M N Z

BCP Bit compare A, Memory tst (A . M) A M N Z

BRES Bit Reset bres Byte, #3 M

BSET Bit Set bset Byte, #3 M

BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C

BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C

CALL Call subroutine

CALLR Call subroutine relative

CLR Clear reg, M 0 1

CP Arithmetic Compare tst(Reg - M) reg M N Z C

CPL One Complement A = FFH-A reg, M N Z 1

DEC Decrement dec Y reg, M N Z

HALT Halt 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

INC Increment inc X reg, M N Z

JP Absolute Jump jp [TBL.w]

JRA Jump relative always

JRT Jump relative

JRF Never jump jrf *

JRIH Jump if ext. INT pin = 1 (ext. INT pin high)

JRIL Jump if ext. INT pin = 0 (ext. INT pin low)

JRH Jump if H = 1 H = 1 ?

JRNH Jump if H = 0 H = 0 ?

JRM Jump if I1:0 = 11 I1:0 = 11 ?

JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?

JRMI Jump if N = 1 (minus) N = 1 ?

JRPL Jump if N = 0 (plus) N = 0 ?

JREQ Jump if Z = 1 (equal) Z = 1 ?

JRNE Jump if Z = 0 (not equal) Z = 0 ?

JRC Jump if C = 1 C = 1 ?

JRNC Jump if C = 0 C = 0 ?

JRULT Jump if C = 1 Unsigned <

JRUGE Jump if C = 0 Jmp if unsigned >=

JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2's compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A = A + M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M I1 H I0 N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C = 0 0

RET Subroutine Return

RIM Enable Interrupts I1:0 = 10 (level 0) 1 0

RLC Rotate left true C C <= A <= C reg, M N Z C

RRC Rotate right true C C => A => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Substract with Carry A = A - M - C A M N Z C

SCF Set carry flag C = 1 1

SIM Disable Interrupts I1:0 = 11 (level 3) 1 1

SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C

SLL Shift left Logic C <= A <= 0 reg, M N Z C

SRL Shift right Logic 0 => A => C reg, M 0 Z C

SRA Shift right Arithmetic A7 => A => C reg, M N Z C

SUB Substraction A = A - M A M N Z C

SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1 1

WFI Wait for Interrupt 1 0

XOR Exclusive OR A = A XOR M A M N Z

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12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-

ferred to VSS.

12.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and max-

imum values are guaranteed in the worst condi-

tions of ambient temperature, supply voltage and

frequencies by tests in production on 100% of the

devices with an ambient temperature at TA=25°C

and TA=TAmax (given by the selected temperature

range).

Data based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. Based on characterization, the min-

imum and maximum values refer to sample tests

and represent the mean value plus or minus three

times the standard deviation (mean±3Σ).

12.1.2 Typical values

Unless otherwise specified, typical data are based

on TA=25°C, VDD=5V. They are given only as de-

sign guidelines and are not tested.

12.1.3 Typical curves

Unless otherwise specified, all typical curves are

given only as design guidelines and are not tested.

12.1.4 Loading capacitor

The loading conditions used for pin parameter

measurement are shown in Figure 128.

Figure 128. Pin loading conditions

12.1.5 Pin input voltage

The input voltage measurement on a pin of the de-

vice is described in Figure 129.

Figure 129. Pin input voltage

ST7 PIN

VIN

ST7 PIN

To guar £7

ST7MC1xx/ST7MC2xx

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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

12.2.1 Voltage Characteristics

12.2.2 Current Characteristics

Notes:

1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.

2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS.

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy with VDD=5.0V” on

page 284.

For best reliability, it is recommended to avoid negative injection of more than 1.6mA

5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-

mum current injection on four I/O port pins of the device.

Symbol Ratings Maximum value Unit

VDD - VSS Supply voltage 6.5

VVPP - VSS Programming Voltage 13

VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3

|ΔVDDx| and |ΔVSSx| Variations between different digital power pins 50 mV

|VSSA - VSSx| Variations between digital and analog ground pins 50

VESD(HBM) Electro-static discharge voltage (Human Body Model)

see section 12.7.3 on page 263

VESD(CDM) Electro-static discharge voltage

(Charged Device Model)

Symbol Ratings Maximum value Unit

IVDD Total current into VDD power lines

(source) 3)

32-pin devices 75

44-pin devices 125

56, 64, 80-pin

devices 175

IVSS Total current out of VSS ground lines

(sink) 3)

32-pin devices 75

44-pin devices 125

56, 64, 80-pin

devices 175

IIO

Output current sunk by any standard I/O and control pin 25

Output current sunk by any high sink I/O pin 50

Output current source by any I/Os and control pin - 25

IINJ(PIN) 2) & 4)

Injected current on VPP pin ± 5

Injected current on RESET pin ± 5

Injected current on OSC1 and OSC2 pins ± 5

Injected current on any other pin 5) ± 5

ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 20

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ABSOLUTE MAXIMUM RATINGS (Cont’d)

12.2.3 Thermal Characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJMaximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)

CPU

ST7MC1xx/ST7MC2xx

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12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions

Figure 130. fCPU Max Versus VDD

Note 1: Clock Detector, ADC, comparator and OPAMP functionalities guaranteed only within 4.5-5.5V

voltage range.

Note:

Some temperature ranges are only available with a specific package and memory size. Refer to Ordering

Information.

Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.

Symbol Parameter Conditions Min Max Unit

fCPU Internal clock frequency versus VDD 08MHz

VDD

Extended operating voltage No Flash Write/Erase. Analog

parameters not guaranteed 1) 3.8 5.5

Standard operating voltage 4.5 5.5

Operating voltage for flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5

TAAmbient temperature range 6 Suffix Version -40 85 °C

C Suffix Version -40 125

fCPU [MHz]

SUPPLY VOLTAGE [V]

3.5 4.0 4.5 5.5

FUNCTIONALITY

GUARANTEED

IN THIS AREA

NOT GUARANTEED

IN THIS AREA

3.8

(UNLESS

OTHERWISE

SPECIFIED

IN THE TABLES

OF PARAMETRIC

DATA)

ST7MC1xx/ST7MC2xx

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OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fOSC, and TA.

Notes:

1. Data based on characterization results, not tested in production.

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating condition for VDD, fOSC, and TA.

Notes:

1. Data based on characterization results, not tested in production.

2. See “MAXIMUM VALUES OF AVD THRESHOLDS” on page 304..

Symbol Parameter Conditions Min Typ Max Unit

VIT+(LVD) Reset release threshold

(VDD rise) 3.90 4.20 4.50

VIT-(LVD) Reset generation threshold

(VDD fall) 3.80 4.00 4.35

Vhys(LVD) LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV

VtPOR VDD rise time rate 1) 20 μs/V

100 ms/V

tg(VDD) Width of filtered glitches on VDD 1)

(which are not detected by the LVD) 40 ns

Symbol Parameter Conditions Min Typ Max2) Unit

VIT+(AVD) 1⇒0 AVDF flag toggle threshold

(VDD rise) 4.35 4.70 4.90

VIT-(AVD) 0⇒1 AVDF flag toggle threshold

(VDD fall) 4.20 4.50 4.70

Vhyst(AVD) AVD voltage threshold hysteresis1) VIT+(AVD)-VIT-(AVD) 200 mV

ΔVIT-

Voltage drop between AVD flag set

and LVD reset activated)VIT-(AVD)-VIT-(LVD) 450 mV

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12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature

range does not take into account the clock source current consumption. To get the total device consump-

tion, the two current values must be added (except for Halt mode for which the clock is stopped).

12.4.1 Run and Slow modes (Flash devices)

Figure 131. Typical IDD in Run vs. fCPU Figure 132. Typical IDD in Slow vs. fCPU

Notes:

1. Data based on characterization results, tested in production at VDD max. and fCPU max.

2. Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash

is 50%.

- All I/O pins in input mode with a static value at VDD or VSS (no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In Slow and Slow-wait mode, fCPU is based on fOSC divided by 32.

To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power

consumption.

Symbol Parameter Conditions Typ Max 1) Unit

IDD

Supply current in Run mode 2)

(see Figure 131)

4.5V≤VDD≤5.5V

fOSC=16MHz, fCPU=8MHz 12 18 mA

Supply current in Slow mode 2)

(see Figure 132)fOSC=16MHz, fCPU=500kHz 5 8 mA

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

012345678

Fcp u Mhz

Idd (mA)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

012345678

Fcp u Mhz

Idd (mA)

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.2 Wait and Slow-wait Modes

Figure 133. Typical IDD in Wait vs. fCPU Figure 134. Typical IDD in Slow-wait vs. fCPU

Notes:

1. Data based on characterization results, tested in production at VDD max. and fCPU max.

2. Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash

is 50%.

- All I/O pins in input mode with a static value at VDD or VSS (no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In Slow and Slow-wait mode, fCPU is based on fOSC divided by 32.

To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power

consumption.

Symbol Parameter Conditions Typ Max 1) Unit

IDD

Supply current in Wait mode 2)

(see Figure 133)

4.5V≤VDD≤5.5V

fOSC=16MHz, fCPU=8MHz 812

Supply current in Slow-wait mode 2)

(see Figure 134)fOSC=16MHz, fCPU=500kHz 3.5 5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

012345678

Fcpu Mhz

Idd (mA)

0.0

0.5

1.0

1.5

2.0

2.5

012345678

Fcpu M hz

Idd (mA)

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 Halt and Active-halt modes

1. All I/O pins in push-pull output mode (when applicable) with a static value at VDD or VSS (no load), PLL and LVD dis-

abled. Data based on characterization results, tested in production at VDD max. and fCPU max.

2. All I/O pins in input mode with a static value at VDD or VSS. Tested in production at VDD max and fcpu max with clock

input OSC1 driven by an external square wave; VDD applied on OSC2 to reduce oscillator consumption. Consumption

may be slightly different with a quartz or resonator.

12.4.4 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over temperature

range does not take into account the clock source current consumption. To get the total device consump-

tion, the two current values must be added (except for Halt mode).

Symbol Parameter Conditions Typ Max Unit

IDD

Supply current in Halt mode 1) VDD=5.5V -40°C≤TA≤+85°C 110 μA

-40°C≤TA≤+125°C 50

Supply current in Active-halt mode 2) 16Mhz external clock 1 1.5 mA

Symbol Parameter Conditions Typ Max Unit

IDD(LVD) LVD supply current Halt mode 180 280 μA

IDD(PLL) PLL supply current VDD = 5V 700

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.5 On-Chip Peripherals

Notes:

1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer

counter stopped (only TIMD bit set). Data valid for one timer.

2. Data based on a differential IDD measurement betwwen reset configuration (timer stopped) and timer counter enable

(only TCE bit set)

3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master

communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption.

4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-

mit sequence.

5. Data based on a differential IDD measurement between reset configuration (motor control disabled) and the whole mo-

tor control cell enable in speed measurement mode. MCO outputs are not validated.

6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

7. Data based on a differential measurement between reset configuration (OPAMP disabled) and amplification of a sin-

ewave (no load, AVCL=1, VDD=5V).

Symbol Parameter Conditions Typ Unit

IDD(TIM) 16-bit Timer supply current 1) fCPU=8MHz VDD=5.0V 50

μA

IDD(ART) ART PWM supply current 2) fCPU=8MHz VDD=5.0V 75

IDD(SPI) SPI supply current 3) fCPU=8MHz VDD=5.0V 400

IDD(SCI) SCI supply current 4) fCPU=8MHz VDD=5.0V 400

IDD(MTC) MTC supply current 5) fCPU=8MHz VDD=5.0V 500

IDD(ADC) ADC supply current when converting 6) fADC=4MHz VDD=5.0V 400

IDD(OPAMP) OPAMP supply current 7) fCPU=8MHz VDD=5.0V 1500

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12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

12.5.1 General Timings

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

12.5.2 External Clock Source

Figure 135. Typical Application with an External Clock Source

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

Symbol Parameter Conditions Min Typ 1) Max Unit

tc(INST) Instruction cycle time 2312t

CPU

fCPU=8MHz 250 375 1500 ns

tv(IT) Interrupt reaction time 2)

tv(IT) = Δtc(INST) + 10

10 22 tCPU

fCPU=8MHz 1.25 2.75 μs

Symbol Parameter Conditions Min Typ Max Unit

VOSC1H OSC1 input pin high level voltage

see Figure 135

0.7xVDD VDD V

VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD

tw(OSC1H)

tw(OSC1L) OSC1 high or low time 1) 25

tr(OSC1)

tf(OSC1) OSC1 rise or fall time 1) 5

ILOSCx Input leakage current VSS≤VIN≤VDD ± 1 μA

OSC1

OSC2

fOSC

EXTERNAL

ST7FMC

CLOCK SOURCE

VOSC1L

VOSC1H

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

90%

10%

VDD

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four

different Crystal/Ceramic resonator oscillators. All

the information given in this paragraph are based

on characterization results with specified typical

external components. In the application, the reso-

nator and the load capacitors have to be placed as

close as possible to the oscillator pins in order to

minimize output distortion and start-up stabiliza-

tion time. Refer to the crystal/ceramic resonator

manufacturer for more details (frequency, pack-

age, accuracy...).

Figure 136. Typical Application with a Crystal or Ceramic Resonator

Notes:

1. When PLL is used, please refer to the PLL characteristics chapter and to the “supply, reset and clock management”

description chapter (fOSC min. is 8 Mhz with PLL).

2. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators,

please consult www.murata.com

3. SMD = [-R0: Plastic tape package (ý =180mm), -B0: Bulk]

LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]

Symbol Parameter Conditions Min Typ Max Unit

fOSC Oscillator Frequency 1) 416MHz

RFFeedback resistor 92 kΩ

CL1

CL2

Recommended load capacitance ver-

sus equivalent serial resistance of the

crystal or ceramic resonator (RS)

See table below pF

Supplier fOSC

(MHz)

Typical Ceramic Resonators2) CL1

[pF]

CL2

[pF]

Reference 3)

Murata

4CSTCR4M00G53-R0 (15) (15)

8CSTCE8M00G52-R0 (10) (10)

16 CSTCE16M0V53-R0 (15) (15)

OSC2

OSC1

fOSC

CL1

CL2

ST7FMC

RESONATOR

WHEN RESONATOR WITH

INTEGRATED CAPACITORS

ST7MC1xx/ST7MC2xx

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.4 Clock Security System with PLL

Table 88. PLL Characteristics

Table 89. Clock Detector Characteristics

Notes:

1. Data based on characterization results, not tested in production.

Symbol Parameter Min Typ Max Unit

fOSC PLL input frequency range 7 8 MHz

Output Frequency Output frequency when the PLL attain lock. 16 MHz

tLock PLL Lock Time (LOCKED = 1) 50 100 μs

Jitter Jitter in the output clock 2 %

fCPU

CPU clock frequency when VCO is con-

nected to ground (ICD internal clock or

back up oscillator ) 3MHz

Symbol Parameter Min Typ Max Unit

fDetect Detected Minimum Input Frequency 500 1) KHz

tsetup Time needed to detect OSCIN once CKD is

enabled 3μs

thold Time needed to detect that OSCIN stops 3 μs

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Figure 137. PLL And Clock Detector Signal Start Up Sequence

Notes:

1. Lock does not go low without resetting the PLLEN bit.

2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of tlock must have

elapsed.

3. 2 clock cycles are missing after CKSEL = 1

4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1).

OSCIN

PLLEN

PLL CLOCK

LOCK

fCLK

t lock

CSSD

CSSIE

INTERRUPT

t setup t hold

16Mhz 6 Mhz fVCO=

OSCIN Clock

PLL clock

CKSEL2)

(PLL and CKD)

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12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers

12.6.2 FLASH Memory

Notes:

1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in hardware registers

(only in Halt mode). Not tested in production.

2. Data based on characterization results, not tested in production.

3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.

4. Data based on simulation results, not tested in production

5. In Write/Erase mode the IDD supply current consumption is the same as in Run mode (section 12.4.1 on page 252)

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode 1) Halt mode (or RESET) 1.6 V

DUAL VOLTAGE HDFLASH MEMORY

Symbol Parameter Conditions Min 2) Typ Max 2) Unit

fCPU Operating frequency Read mode 0 8 MHz

Write / Erase mode 1 8

VPP Programming voltage 3) 4.5V ≤ VDD ≤ 5.5V 11.4 12.6 V

IPP VPP current4) 5) Read (VPP=12V) 200 µA

Write / Erase 30 mA

tVPP Internal VPP stabilization time 10 μs

tRET Data retention

TA=85°C 40

yearsTA=105°C 15

TA=125°C 7

NRW Write erase cycles TA=25°C 100 cycles

TPROG

TERASE

Programming or erasing tempera-

ture range -40 25 85 °C

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12.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-

sis during product characterization.

12.7.1 Functional EMS (Electro Magnetic

Susceptibility)

Based on a simple running application on the

product (toggling 2 LEDs through I/O ports), the

product is stressed by two electro magnetic events

until a failure occurs (indicated by the LEDs).

■ESD: Electro-Static Discharge (positive and

negative) is applied on all pins of the device until

a functional disturbance occurs. This test

conforms with the IEC 1000-4-2 standard.

■FTB: A Burst of Fast Transient voltage (positive

and negative) is applied to VDD and VSS through

a 100pF capacitor, until a functional disturbance

occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be re-

sumed. The test results are given in the table be-

low based on the EMS levels and classes defined

in application note AN1709.

12.7.1.1 Designing hardened software to avoid

noise problems

EMC characterization and optimization are per-

formed at component level with a typical applica-

tion environment and simplified MCU software. It

should be noted that good EMC performance is

highly dependent on the user application and the

software in particular.

Therefore it is recommended that the user applies

EMC software optimization and prequalification

tests in relation with the EMC level requested for

his application.

Software recommendations:

The software flowchart must include the manage-

ment of runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset

and program counter corruption) can be repro-

duced by manually forcing a low state on the RE-

SET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be ap-

plied directly on the device, over the range of

specification values. When unexpected behaviour

is detected, the software can be hardened to pre-

vent unrecoverable errors occurring (see applica-

tion note AN1015).

Symbol Parameter Conditions Level/

Class

VFESD

Voltage limits to be applied on

any I/O pin to induce a function-

al disturbance

Flash/ROM devices

VDD=5V, TA=+25°C,

fOSC=8MHz, LVD OFF

conforms to IEC 1000-4-2

VDD=5V, TA=+25°C,

fOSC=8MHz, LVD ON

conforms to IEC 1000-4-2

VFFTB

Fast transient voltage burst lim-

its to be applied through 100pF

on VDD and VDD pins to induce

a functional disturbance

Flash devices VDD=5V, TA=+25°C, fOSC=8MHz,

conforms to IEC 1000-4-4 4A

ROM devices VDD=5V, TA=+25°C, fOSC=8MHz,

conforms to IEC 1000-4-4 3B

£7

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EMC CHARACTERISTICS (Cont’d)

12.7.2 EMI (Electromagnetic interference)

Based on a simple application running on the

product (toggling 2 LEDs through the I/O ports),

the product is monitored in terms of emission. This

emission test is in line with the norm SAE J 1752/

3 which specifies the board and the loading of

each pin.

Notes:

1. Data based on characterization results, not tested in production.

2. Refer to Application Note AN1709 for data on other package types

Symbol Parameter Conditions Device/ Package Monitored

Frequency Band

Max vs. [fOSC/fCPU]Unit

8/4MHz 16/8MHz

SEMI Peak level

VDD=5V,

TA=+25°C

conforming to

SAE J 1752/3

Flash/LQFP64

0.1MHz to 30MHz 8 6

dBμV30MHz to 130MHz 8 12

130MHz to 1GHz 1 9

SAE EMI Level 1.5 2.5 -

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EMC CHARACTERISTICS (Cont’d)

12.7.3 Absolute Maximum Ratings (Electrical

Sensitivity)

Based on two different tests (ESD and LU) using

specific measurement methods, the product is

stressed in order to determine its performance in

terms of electrical sensitivity. For more details, re-

fer to the application note AN1181.

12.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega-

tive pulse separated by 1 second) are applied to

the pins of each sample according to each pin

combination. The sample size depends on the

number of supply pins in the device (3 parts*(n+1)

supply pin). Three models can be simulated: Hu-

man Body Model, Machine Model and Charged

Device Model. This test conforms to the JESD22-

A114A/A115A/C101-A standard.

Absolute Maximum Ratings

Notes:

1. Data based on characterization results, not tested in production.

12.7.3.2 Static Latch-Up

■LU: two complementary static tests are required

on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power

supply pin) and a current injection (applied to

each input, output and configurable I/O pin) are

performed on each sample. This test conforms

to the EIA/JESD 78 IC latch-up standard.

Electrical Sensitivities

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

Symbol Ratings Conditions Maximum value 1) Unit

VESD(HBM) Electro-static discharge voltage

(Human Body Model) TA=+25°C 2000

VESD(CDM) Electro-static discharge voltage

(Charged Device Model) TA=+25°C 250

Symbol Parameter Conditions Class 1)

LU Static latch-up class TA=+25°C

TA=+125°C

£7

ST7MC1xx/ST7MC2xx

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12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS.

Refer to section 12.2.2 on page 248 for more details. For PD7, refer to ‘INJECTED CURRENT ON PD7” on page 303.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 138). Static peak current value taken at a fixed VIN value,

based on design simulation and technology characteristics, not tested in production. This value depends on VDD and tem-

perature values.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 139). This data is based on characterization results, tested in production at VDD max.

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level voltage

CMOS ports

0.3xVDD V

VIH Input high level voltage 0.7xVDD

Vhys Schmitt trigger voltage hysteresis 2) 1V

VIL Input low level voltage

G & H ports

0.8 V

VIH Input high level voltage 2.8

Vhys Schmitt trigger voltage hysteresis 2) 400 mV

IINJ(PIN)3) Injected Current on an I/O

VDD=5V

+5/-2

ΣIINJ(PIN)3

)Total injected current (sum of all I/O

and control pins) ± 25

ILInput leakage current VSS≤VIN≤VDD ±1

μA

ISStatic current consumption induced

by each floating input pin4) Floating input mode 200

RPU Weak pull-up equivalent resistor 5) VIN=VSS 50 90 250 kΩ

CIO I/O pin capacitance 5 pF

tf(IO)out Output high to low level fall time 1) CL=50pF

Between 10% and 90%

25 ns

tr(IO)out Output low to high level rise time 1) 25

tw(IT)in External interrupt pulse time 6) 1t

CPU

'PU VDD IN Vss PU VDD IN Vss

ST7MC1xx/ST7MC2xx

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 138. Two typical Applications with

unused I/O Pin

Figure 139. Typical IPU vs. VDD with VIN=VSS

Figure 140. Typical RPU vs. VDD with VIN=VSS

10kΩUNUSED I/O PORT

ST7MC

10kΩUNUSED I/O PORT

ST7MC

VDD

Note: I/O can be left unconnected if it is configured as output

robustness and lower cost.

(0 or 1) by the software. This has the advantage of greater EMC

3.5 4 4.5 5 5.5

VDD (V)

Pull Up Current (uA)

Temperature

(-45 ºC)

Temperature

(25 ºC)

Temperature

(90 ºC)

Temperature

(130 ºC)

100

150

200

250

300

3.5 4 4.5 5 5.5

VDD (V)

I/O Pull Up Resistor (kohm)

Temperature

(-45 ºC)

Temperature

(25 ºC)

Temperature

(90 ºC)

Temperature

(130 ºC)

ST7MC1xx/ST7MC2xx

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I/O PORT PIN CHARACTERISTICS (Cont’d)

12.8.2 Output Driving Current

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 141. Typical VOL at VDD=5V (standard)

Figure 142. Typical VOL at VDD=5V (high-sink)

Figure 143. Typical VDD-VOH at VDD=5V

Notes:

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD.

Symbol Parameter Conditions Min Max Unit

VOL 1)

Output low level voltage for a standard I/O pin

when 8 pins are sunk at same time

(see Figure 141)

VDD=5V

IIO=+5mA 1.2

IIO=+2mA 0.5

Output low level voltage for a high sink I/O pin

when 4 pins are sunk at same time

(see Figure 142)

IIO=+20mA, TA≤85°C

TA≥85°C

1.3

1.5

IIO=+8mA 0.6

VOH 2) Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(see Figure 143)

IIO=-5mA, TA≤85°C

TA≥85°C VDD-1.4

VDD-1.6

IIO=-2mA VDD-0.7

0246810

Iio [mA]

0.5

1.5

2.5

Vol [V] at Vdd=5V

Ta=-40°C

Ta=25°C

Ta=85°C

Ta=125°C

0 5 10 15 20 25 30

Iio [mA]

0.5

1.5

Vol [V] at Vdd=5V

Ta=-40°C

Ta=25°C

Ta=85°C

Ta=125°C

-8 -6 -4 -2 0

Iio [mA]

Vdd-Voh [V] at Vdd=5V

Ta=-40°C

Ta=25°C

Ta=85°C

Ta=125°C

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12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network protects the device against parasitic resets.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level voltage 0.3xVDD V

VIH Input high level voltage 0.7xVDD

Vhys Schmitt trigger voltage hysteresis 2) 1V

VOL Output low level voltage 3) VDD=5V IIO=+5mA 0.5 1.2 V

IIO=+2mA 0.2 0.5

IIO Driving current on RESET pin 2 mA

RON Weak pull-up equivalent resistor VIN=VSS, VDD=5V 50 80 150 kΩ

tw(RSTL)out Generated reset pulse duration Internal reset sources 30 μs

th(RSTL)in External reset pulse hold time 4) 2.5 μs

tg(RSTL)in Filtered glitch duration 5) 450 ns

In most ned 10 al Heter

ST7MC1xx/ST7MC2xx

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 144. RESET pin protection when LVD is enabled.1)2)3)4)

Figure 145. RESET pin protection when LVD is disabled.1)

Note 1:

– The reset network protects the device against parasitic resets.

– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the

device can be damaged when the ST7 generates an internal reset (LVD, illegal opcode or watchdog).

– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go

below the VIL max. level specified in section 12.9.1 on page 267. Otherwise the reset will not be taken into account

internally.

– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-

sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in

section 12.2.2 on page 248.

Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down

capacitor is required to filter noise on the reset line.

Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET

pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power

consumption of the MCU).

Note 4: Tips when using the LVD:

– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)

– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and

AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.

– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.

In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the

RESET pin with a 5µF to 20µF capacitor.”

Note 5: Please refer to “Illegal Opcode Reset” on page 244 for more details on illegal opcode reset conditions

0.01μF

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

LVD RESET

INTERNAL

RESET

EXTERNAL

Required

1MΩ

Optional

(note 3)

ILLEGAL

OPCODE 5)

0.01μF

EXTERNAL

RESET

CIRCUIT

USER

Required

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

INTERNAL

RESET

ILLEGAL OPCODE 5)

ST7MC1xx/ST7MC2xx

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CONTROL PIN CHARACTERISTICS (Cont’d)

12.9.2 ICCSEL/VPP Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 146. Two typical Applications with VPP Pin 3)

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

2. VPP is also used to program the flash, refer to the Flash characteristics.

3. When the ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.

Symbol Parameter Conditions Min Max Unit

VIL Input low level voltage 1) VSS 0.2 V

VIH Input high level voltage 1) 2) ICC mode entry VDD-0.1 12.6

ILInput leakage current VIN=VSS ±1 μA

ICCSEL/VPP

ST7MC 10kΩ

PROGRAMMING

TOOL

VPP

ST7MC

£7

ST7MC1xx/ST7MC2xx

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12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD,

fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(output compare, input capture, external clock,

PWM output...).

12.10.1 8-Bit PWM-ART Auto-Reload Timer

12.10.2 16-Bit Timer

Symbol Parameter Conditions Min Typ Max Unit

tres(PWM) PWM resolution time 1t

CPU

fCPU=8MHz 125 ns

fEXT ART external clock frequency 0 fCPU/2 MHz

fPWM PWM repetition rate 0 fCPU/2

ResPWM PWM resolution 8bit

VOS PWM/DAC output step voltage VDD=5V, Res=8-bits 20 mV

Symbol Parameter Conditions Min Typ Max Unit

tw(ICAP)in Input capture pulse time 1 tCPU

tres(PWM) PWM resolution time 2t

CPU

fCPU=8MHz 250 ns

fEXT Timer external clock frequency 0 fCPU/4 MHz

fPWM PWM repetition rate 0 fCPU/4 MHz

ResPWM PWM resolution 16 bit

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12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for VDD,

fOSC, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Figure 147. SPI Slave Timing Diagram with CPHA=0 3)

Notes:

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

4. Depends on fCPU. For example, if fCPU=8MHz, then TCPU = 1/fCPU =125ns and tsu(SS)=550ns

Symbol Parameter Conditions Min Max Unit

fSCK

1/tc(SCK) SPI clock frequency

Master

fCPU=8MHz

fCPU/128

0.0625

fCPU/4

2MHz

Slave

fCPU=8MHz 0fCPU/2

tr(SCK)

tf(SCK) SPI clock rise and fall time see I/O port pin description

tsu(SS) 1) SS setup time 4) Slave (4 x TCPU) + 50

th(SS) 1) SS hold time Slave 120

tw(SCKH)

tw(SCKL) SCK high and low time Master

Slave

100

tsu(MI)

tsu(SI) Data input setup time Master

Slave

100

th(MI)

th(SI) Data input hold time Master

Slave

100

ta(SO) Data output access time Slave 0 120

tdis(SO) Data output disable time Slave 240

tv(SO) Data output valid time Slave (after enable edge) 120

th(SO) Data output hold time 0

tv(MO) Data output valid time Master (after enable edge) 120

th(MO) Data output hold time 0

SS INPUT

SCK INPUT

CPHA=0

MOSI INPUT

MISO OUTPUT

CPHA=0

tc(SCK)

tw(SCKH)

tw(SCKL) tr(SCK)

tf(SCK)

tv(SO)

ta(SO)

tsu(SI) th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

seenote2

CPOL=0

CPOL=1

tsu(SS)th(SS)

tdis(SO)

th(SO)

see

note 2

BIT1 IN

ST7MC1xx/ST7MC2xx

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 148. SPI Slave Timing Diagram with CPHA=11)

Figure 149. SPI Master Timing Diagram 1)

Notes:

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

SS INPUT

SCK INPUT

CPHA=1

MOSI INPUT

MISO OUTPUT

CPHA=1

tw(SCKH)

tw(SCKL) tr(SCK)

tf(SCK)

ta(SO)

tsu(SI) th(SI)

MSB OUT BIT6 OUT LSB OUT

see

CPOL=0

CPOL=1

tsu(SS)th(SS)

tdis(SO)

th(SO)

see

note 2note 2

tc(SCK)

tv(SO)

MSB IN LSB IN

BIT1 IN

SS INPUT

SCK INPUT

CPHA = 0

MOSI OUTPUT

MISO INPUT

CPHA = 0

CPHA = 1

tc(SCK)

tw(SCKH)

tw(SCKL)

th(MI)

tsu(MI)

MSB IN

MSB OUT

BIT6 IN

BIT6 OUT LSB OUT

LSB IN

Seenote2 Seenote2

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

tr(SCK)

tf(SCK)

th(MO)

tv(MO)

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12.12 MOTOR CONTROL CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

12.12.1 Internal Reference Voltage

Note:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

Symbol Parameter Conditions Min Typ 1) Max Unit

VREF

Voltage threshold (VR [2:0] = 000) VR [2:0] = 000 VDD*0.04

Example: VDD -VSSA = 5V 0.2

Voltage threshold (VR [2:0] = 001) VR [2:0]= 001 VDD*0.12

Example: VDD -VSSA = 5V 0.6

Voltage threshold (VR [2:0] = 010) VR [2:0] = 010 VDD*0.2

Example: VDD -VSSA = 5V 1.0

Voltage threshold (VR [2:0] = 011) VR [2:0]= 011 VDD*0.3

Example: VDD -VSSA = 5V 1.5

Voltage threshold (VR [2:0] = 100) VR [2:0] = 100 VDD*0.4

Example: VDD -VSSA = 5V 2.0

Voltage threshold (VR [2:0] = 101) VR [2:0]= 101 VDD*0.5

Example: VDD -VSSA = 5V 2.5

Voltage threshold (VR [2:0] = 110) VR [2:0] = 110 VDD*0.7

Example: VDD -VSSA = 5V 3.5

VREF/

VREF Tolerance on VREF 2.5 10 %

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

12.12.2 Input Stage (comparator + sampling)

Note:

1. The comparator accuracy is dependent of the environment. The offset value is given for a comparison done with all

digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care

must be taken to avoid switching on I/Os close to the inputs when the comparator is in use. This phenomenon is even

more critical when a big external serial resistor is added on the inputs.

2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.

3. This delay represents the number of clock cycles needed to generate an event as soon as the comparator output

or MCO outputs change.

Example: In tachogenerator mode, this means that capture is performed on the 4th clock cycle after comparator commu-

tation., i.e. there is a variation of (1/fmtc) or (1 / fSCF) depending on the case.

Symbol Parameter Conditions Min Typ Max Unit

VIN Comparator input volt-

age range VSSA - 0.1 VDD + 0.1 V

Voffset Comparator offset error 5 40 1) mV

Ioffset Input offset current 1μA

tpropag Comparator propagation

delay 35 100 ns

tstartup Start-up filter duration2) Time waited before sampling when com-

parator is turned ON, i.e. CKE=1 or

DAC=1 (with fPERIPH = 4MHz)

3μs

tsampling Digital sampling delay 3)

Time needed to generate a capture in

tachogenerator mode as soon as the MCI

input toggles

4 / fmtc

Time needed to capture MTIM in MZREG

(BEMF) when sampling during PWM sig-

nal OFF time as soon as MCO becomes

3 / fmtc (see Figure 150)

Time needed to set/reset the HST bit

when sampling during PWM signal OFF

time as soon as MCO becomes ON

(BEMF)

1 / fmtc (see Figure 150)

Time needed to generate Z event (MTIM

captured in MZREG) as soon as the com-

parator toggles (when sampling at fSCF)

1 / fSCF + 3 / fmtc (see Figure 151)

Time needed to generate D event (MTIM

captured in MDREG) as soon as the com-

parator toggles

1 / fSCF + 3 / fmtc (see Figure 151)

Time needed to set/reset the HST bit

when sampling during PWM signal ON

time after a delay (DS>0) as soon as

MCO becomes ON

Delay programmed in DS bits

(MCONF) +1 / fmtc

(see Figure 152)

Time needed to generate Z event (MTIM

in MZREG) when sampling during PWM

signal ON time after a delay (DS>0) as

soon as MCO becomes ON

Delay programmed in DS bits

(MCONF)

+ 3 / fmtc

(see Figure 152)

Time needed to generate Z event (MTIM

captured in MZREG) when sampling dur-

ing PWM signal ON time at fSCF after a

delay (DS>0)

Delay programmed in DS bits

(MCONF)

+ 1 / fSCF + 3 / fmtc

(see Figure 152)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

Figure 150. Example 1: Waveforms for Zero-crossing Detection with Sampling at the end of PWM

off-time

Figure 151. Example 2: Waveforms for Zero-crossing Detection with Sampling at fSCF

fmtc

MCOx

Comparator

Output

HST (MCRC)

MTIM

MZREG

A5 A6 A7

XX A5

Sampling time

Sample

fmtc

fSCF

Comparator

Output

HST (MCRC)

MTIM

MZREG

A5 A6 A7

XX A6

Sampling time

Sample

ST7MC1xx/ST7MC2xx

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

Figure 152. Example 3: Waveforms for Zero-crossing Detection with Sampling after a Delay during

PWM On-time

Figure 153. Example 4: Waveforms for zero-crossing detection with sampling after a delay

at fSCF

fmtc

MCOx

Comparator

output

HST (MCRC)

MTIM

MZREG

A5 A6 A7

XX A6

Sampling time

sample Delay from DS bits

fmtc

fSCF

comparator

output

HST (MCRC)

MTIM

MZREG

A5 A6 A7

XX A7

Sampling time

sample

MCOx

Delay from DS bits

ST7MC1xx/ST7MC2xx

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

Figure 154. Example 5: Waveforms for sensor HST update timing diagram for a newly selected

phase input

fmtc

fSCF

Comparator

output

HST (MCRC)

Sampling time

sample

write IS[1:0] = 01

= 2 x fcpu

MCIx

Sampling of sensor input is done at fSCF, so after writing IS[1:0] in the MPHST register

for input selection, you have to wait:

1) 1/fmtc to resynchronize the data and set the MCIx bit

2) 100ns corresponding to the comparator & multiplexer propagation delay (d)

3) 1/fSCF to sample the comparator output

4) 1/fmtc to resynchronize the data and set the HST bit

Example with fPERIPH = fmtc = 4MHz :

SCF[1:0] 00 01 10 11

fSCF

Secure

waiting

time

to read HST

1MHz 500kHz 250kHz 125kHz

2µs 3µs 5µs 9µs

IS[1:0] (MPHST)

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

12.12.3 Input Stage (Current Feedback Comparator + Sampling)

Notes:

1. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of

the comparator and must be avoided:

– Negative injection current on the I/Os close to the comparator inputs

– Switching on I/Os close to the comparator inputs

– Negative injection current on not used comparator input (MCCFI0 or MCCFI1)

– Switching with a high dV/dt on not used comparator input (MCCFI0 or MCCFI1)

These phenomena are even more critical when a big external serial resistor is added on the inputs.

2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.

3.This delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput chang-

es.

Example: When CFF=0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle

after comparator commutation, i.e. there is a variation of (1/fmtc) or (4 / fPERIPH) depending on the case.

Symbol Parameter Conditions Min Typ Max Unit

VIN Comparator input voltage range VSSA - 0.1 VDD + 0.1 V

Voffset Comparator offset error 5 40 1) mV

Ioffset Input offset current 1μA

tpropag Comparator propagation

delay 1) 35 100 ns

tstartup Start-up filter duration 2)

Time waited before sampling

when comparator is turned

ON, i.e. CKE=1 or DAC=1

(with fPERIPH = 4MHz)

3μs

tsampling Digital sampling delay 3)

Time needed to turn OFF the

MCOs when comparator out-

put rises (CFF=0)

4 / f MTC (see Figure 155)

Time between a comparator

toggle (current loop event)

and bit CL becoming set

(CFF=0)

2 / f MTC (see Figure 155)

Time needed to turn OFF the

MCOs when comparator out-

put rises (CFF=x)

(1+x) * (4 / fPERIPH) + (3 / fmtc)

(see Figure 156)

Time between a comparator

toggle (current loop event)

and bit CL becoming set

(CFF=x)

(1+x) * (4 / fPERIPH) + (1 / fmtc)

(see Figure 156)

ST7MC1xx/ST7MC2xx

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MOTOR CONTROL CHARACTERISTICS (Cont’d)

Figure 155. Example 1: Waveforms For Overcurrent Detection with Current Feedback Filter OFF

Figure 156. Example 2: waveforms for overcurrent detection with current feedback filter ON

(CFF=001 => 2 consecutive samples are needed to validate the overcurrent event)

fmtc

MCOx

Comparator

Output

CL (MCRC)

Sampling time

Sample

fmtc

fPERIPH/4

Comparator

Output

CL (MCRC)

Sampling time

Sample

MCOx

ST7MC1xx/ST7MC2xx

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12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS

Subject to general operating conditions for fOSC, and TA unless otherwise specified.

(TA = -40..+125oC, VDD-VSSA = 4.5..5.5V unless otherwise specified

Note:

1. AVCL = closed loop gain

2. Data based on characterization results, not tested in production.

3. after offset compensation has been performed.

4. The amplifier accuracy is dependent on the environment. The offset value is given for a measurement done with all

digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care

must be taken to avoid switching on I/Os close to the inputs when the opamp is in use. This phenomenon is even more

critical when a big external serial resistor is added on the inputs.

5. The Data provided from simulations (not tested in production) to guide the user when re-calibration is needed.

6. The Data provided from simulations (not tested in production).

Symbol Parameter Conditions Min Typ Max Unit

RLResistive Load (max 500µA @

5V) 10 kΩ

CLCapacitive Load at VOUT pin 150 pF

VCMIR Common Mode Input Range VSSA VDD/2 V

Vio Input Offset Voltage ( + or - ) 3) After calibration, VIC =1V 2.5 10 4) mV

ΔVio

Input Offset Voltage Drift from

the calibrated Voltage, temper-

ature conditions

with respect to temperature 8.5 5) μV/oC

with respect to common mode input 1 5) mV/V

with respect to supply 3.1 5) mV/V

CMR Common Mode Rejection

Ratio HIGHGAIN=0 @ 100kHz 74 dB

SVR Supply Voltage Rejection

Ratio @ 100kHz 502) 65 dB

Avd Voltage Gain RL=10kΩ(1.5)2) 12 V/mV

VSAT_OH High Level Output Saturation

Voltage (VDD-VOUT)RL=10kΩ60 90 2) mV

VSAT_OL Low Level Output Saturation

Voltage RL=10kΩ30 90 2) mV

GBP Gain Bandwidth Product

VOAP = VDD / 2, measured at

0dB gain, feedback resistor

ratio = 10 (20dB inverting con-

figuration)

HIGHGAIN=0 1.3 2) 1.5 2 2)

MHz

HIGHGAIN=1 2.6 2) 34

SR+Slew Rate while rising

HIGHGAIN=0

(AVCL=1, RL=10kΩ, CL=150pF, Vi=1.75V to

2.75V) 1)

12) 2V/μs

SR-Slew Rate while falling

HIGHGAIN=0

(AVCL=1, RL=10kΩ, CL=150pF, Vi=1.75V to

2.75V) 1)

2.52) 7.5 V/μs

Φm Phase Margin HIGHGAIN=0 73 degrees

HIGHGAIN=1 75

Twakeup Wakeup time for the opamp

from off state 0.8 6) 1.6 6) μs

AIN IADC AIN CAIN AIM values. '\\ : \\ & E]

ST7MC1xx/ST7MC2xx

281/309

12.14 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 157. RAIN max. vs fADC with CAIN=0pF3) Figure 158. Recommended CAIN & RAIN values.4)

Symbol Parameter Conditions Min Typ Max Unit

VAREF Analog Reference Voltage 3 VDD V

fADC ADC clock frequency 4 MHz

VAIN Conversion voltage range 1) VSSA VAREF V

Ilkg

Positive input leakage current for

analog input ±1 μA

Negative input leakage current on

analog pins

VIN<VSS, | IIN |< 400µA on

adjacent analog pin 56μA

RAIN External input impedance see

Figure

157 and

Figure

158 2)3)4)

kΩ

CAIN External capacitor on analog input pF

fAIN Variation freq. of analog input signal Hz

CADC Internal sample and hold capacitor 6 pF

tADC

Conversion time (Sample+Hold) fCPU=8MHz, fADC=4MHz,

ADSTS bit in MCCBCR

3.5 μs

- Sample capacitor loading time

- Hold conversion time

10 1/fADC

Conversion time (Sample+Hold) fCPU=8MHz, fADC=4MHz,

ADSTS bit in MCCBCR

6.5 μs

- Sample capacitor loading time

- Hold conversion time

10 1/fADC

RAREF Analog Reference Input Resistor 11 kΩ

0103070

CPARASITIC (pF)

Max. RAIN (Kohm)

2 MHz

1 MHz

0.1

100

1000

0.01 0.1 1 10

fAIN(KHz)

Max. RAIN (Kohm)

Cain 10 nF

Cain 22 nF

Cain 47 nF

ST7MC1xx/ST7MC2xx

282/309

10-BIT ADC CHARACTERISTICS (Cont’d)

Figure 159. Typical Application with ADC

Notes:

1. When VSSA pins are not available on the pinout, the ADC refer to VSS.

2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN).

AINx

ST7MC

VDD

±1μA

0.6V

VAIN

RAIN

VAREF

VSSA

0.1μF

VDD

RAREF

CADC

6pF

CAIN

10-Bit A/D

Conversion

2kΩ(max)

ST7MC1xx/ST7MC2xx

283/309

10-BIT ADC CHARACTERISTICS (Cont’d)

12.14.1 Analog Power Supply and Reference

Pins

Depending on the MCU pin count, the package

may feature separate VAREF and VSSA analog

power supply pins. These pins supply power to the

A/D converter cell and function as the high and low

reference voltages for the conversion. In some

packages, VAREF and VSSA pins are not available

(refer to section 2 on page 6). In this case the an-

alog supply and reference pads are internally

bonded to the VDD and VSS pins.

Separation of the digital and analog power pins al-

low board designers to improve A/D performance.

Conversion accuracy can be impacted by voltage

drops and noise in the event of heavily loaded or

badly decoupled power supply lines (see Section

12.14.2 General PCB Design Guidelines).

12.14.2 General PCB Design Guidelines

To obtain best results, some general design and

layout rules should be followed when designing

the application PCB to shield the noise-sensitive,

analog physical interface from noise-generating

CMOS logic signals.

– Use separate digital and analog planes. The an-

alog ground plane should be connected to the

digital ground plane via a single point on the

PCB.

– Filter power to the analog power planes. It is rec-

ommended to connect capacitors, with good high

frequency characteristics, between the power

and ground lines, placing 0.1µF and optionally, if

needed 10pF capacitors as close as possible to

the ST7 power supply pins and a 1 to 10µF ca-

pacitor close to the power source (see Figure

160).

– The analog and digital power supplies should be

connected in a star network. Do not use a resis-

tor, as VAREF is used as a reference voltage by

the A/D converter and any resistance would

cause a voltage drop and a loss of accuracy.

– Properly place components and route the signal

traces on the PCB to shield the analog inputs.

Analog signals paths should run over the analog

ground plane and be as short as possible. Isolate

analog signals from digital signals that may

switch while the analog inputs are being sampled

by the A/D converter. Do not toggle digital out-

puts on the same I/O port as the A/D input being

converted.

Figure 160. Power Supply Filtering

VSS

VDD

0.1μF

10pF

VDD

ST7MC

VAREF

VSSA

POWER

SUPPLY

SOURCE

ST7

DIGITAL NOISE

FILTERING

EXTERNAL

NOISE

FILTERING

1 to 10μF

0.1μF

10pF

(if needed)

ST7MC1xx/ST7MC2xx

284/309

10-BIT ADC CHARACTERISTICS (Cont’d)

ADC Accuracy with VDD=5.0V

Notes:

1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion

being performed on another analog input. The effect of negative injection current on analog pins is specified in Section

12.14.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC

accuracy.

2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C

to 125°C (± 3σ distribution limits).

Figure 161. ADC Accuracy Characteristics

Notes:

1. ADC Accuracy vs. Negative Injection Current:

For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 4 LSB

for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed

under worst-case conditions for injection:

- negative injection

- injection to an Input with analog capability, adjacent to the enabled Analog Input

- at 5V VDD supply, and worst case temperature.

2. Data based on characterization results with TA=25°C.

3. Data based on characterization results over the whole temperature range, monitored in production.

Symbol Parameter Conditions Typ Max 2) Unit

|ET| Total unadjusted error 1)

VAREF=3.0V to 5.0V, fCPU=8MHz,

fADC=4MHz, RAIN<10kΩ

LSB

|EO|Offset error

1) 2.5 4

|EG| Gain Error 1) 24

|ED| Differential linearity error 1) 24.5

|EL| Integral linearity error 1) 24.5

1LSB

IDEAL

1LSBIDEAL

VDDA VSSA

–

1024

-----------------------------------------=

Vin (LSBIDEAL)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Error: deviation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

Digital Result ADCDR

1023

1022

1021

1234567 1021 1022 1023 1024

(1)

(2)

(3)

VAREF

VSSA

Immmmmmmmmmmmmmmmmmm O .. HHHHHHHHHHHHHHHHHHHH

ST7MC1xx/ST7MC2xx

285/309

13 PACKAGE CHARACTERISTICS

In order to meet environmental requirements, ST

offers these devices in different grades of ECO-

PACK® packages, depending on their level of en-

vironmental compliance. ECOPACK® specifica-

tions, grade definitions and product status are

available at: www.st.com. ECOPACK® is an ST

trademark.

13.1 PACKAGE MECHANICAL DATA

Figure 162. 80-Pin Low Profile Quad Flat Package

Dim. mm inches1)

Min Typ Max Min Typ Max

A 1.60 0.0630

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b0.22 0.32 0.38 0.0087 0.0126 0.0150

C0.09 0.20 0.0035 0.0079

D 16.00 0.6299

D1 14.00 0.5512

E 16.00 0.6299

E1 14.00 0.5512

e0.65 0.0256

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

Number of Pins

N80

EE1

HHHHHHHHHHHHHHHH O HHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHR, HHHHHHHHHHH 1 HHHHHHHHHH O HHHHHHHHHHH—,

ST7MC1xx/ST7MC2xx

286/309

PACKAGE CHARACTERISTICS (Cont’d)

Figure 163. 64-Pin Low Profile Quad Flat Package (14x14)

Figure 164. 44-Pin Low Profile Quad Flat Package

5PACKAGE CHARACTERISTICS (Cont’d) 6

Dim. mm inches1)

Min Typ Max Min Typ Max

A 1.60 0.0630

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b0.30 0.37 0.45 0.0118 0.0146 0.0177

c0.09 0.20 0.0035 0.0079

D 16.00 0.6299

D1 14.00 0.5512

E 16.00 0.6299

E1 14.00 0.5512

e0.80 0.0315

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

Number of Pins

N64

Note 1. Values in inches are converted from mm

and rounded to 4 decimal digits.

Dim. mm inches1)

Note 1. Values in inches are converted from mm

and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A 1.60 0.0630

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b0.30 0.37 0.45 0.0118 0.0146 0.0177

C0.09 0.20 0.0035 0.0079

D 12.00 0.4724

D1 10.00 0.3937

E 12.00 0.4724

E1 10.00 0.3937

e0.80 0.0315

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

Number of Pins

N44

HHHHHHHH HHHHHHHH O HHHHHHHH E]

ST7MC1xx/ST7MC2xx

287/309

PACKAGE CHARACTERISTICS (Cont’d)

Figure 165. 32-Pin Low Profile Quad Flat Package

Figure 166. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

Dim. mm inches1)

Min Typ Max Min Typ Max

A 1.60 0.0630

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b0.30 0.37 0.45 0.0118 0.0146 0.0177

C0.09 0.20 0.0035 0.0079

D 9.00 0.3543

D1 7.00 0.2756

E 9.00 0.3543

E1 7.00 0.2756

e0.80 0.0315

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

Number of Pins

N32

Note 1. Values in inches are converted from mm

and rounded to 4 decimal digits.

Dim. mm inches1)

Note 1. Values in inches are converted from mm

and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A6.35 0.2500

A1 0.38 0.0150

A2 3.18 4.95 0.1252 0.1949

b0.41 0.0161

b2 0.89 0.0350

C0.20 0.38 0.0079 0.0150

D50.29 53.21 1.9799 2.0949

E15.01 0.5909

E1 12.32 14.73 0.4850 0.5799

e1.78 0.0701

eA 15.24 0.6000

eB 17.78 0.7000

L2.92 5.08 0.1150 0.2000

Number of Pins

N56

0.015

GAGE PLANE

ST7MC1xx/ST7MC2xx

288/309

PACKAGE CHARACTERISTICS (Cont’d)

13.2 THERMAL CHARACTERISTICS

Notes:

1. The maximum chip-junction temperature is based on technology characteristics.

2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.

The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT

where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on

the ports used in the application.

Symbol Ratings Value Unit

RthJA

Package thermal resistance (junction to ambient)

LQFP80 14x14

LQFP64 14x14

LQFP44 10x10

LQFP32 7x7

SDIP32 400mil

SDIP56 600mil

°C/W

TJmax Maximum junction temperature1) 150 °C

PDmax Power dissipation 2) 500 mW

ST7MC1xx/ST7MC2xx

289/309

13.3 SOLDERING INFORMATION

In accordance with the RoHS European directive,

all STMicroelectronics packages have been con-

verted to lead-free technology, named ECO-

PACKTM.

■ECOPACKTM packages are qualified according

to the JEDEC STD-020C compliant soldering

profile.

■Detailed information on the STMicroelectronics

ECOPACKTM transition program is available on

www.st.com/stonline/leadfree/, with specific

technical Application notes covering the main

technical aspects related to lead-free

conversion (AN2033, AN2034, AN2035,

AN2036).

Backward and forward compatibility:

The main difference between Pb and Pb-free sol-

dering process is the temperature range.

– ECOPACKTM LQFP, SDIP and SO packages

are fully compatible with Lead (Pb) containing

soldering process (see application note AN2034)

– LQFP, SDIP and SO Pb-packages are compati-

ble with Lead-free soldering process, neverthe-

less it's the customer's duty to verify that the Pb-

packages maximum temperature (mentioned on

the Inner box label) is compatible with their Lead-

free soldering temperature.

Table 90. Soldering Compatibility (wave and reflow soldering process)

* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)

is compatible with their Lead-free soldering process.

Package Plating material devices Pb solder paste Pb-free solder paste

SDIP & PDIP Sn (pure Tin) Yes Yes *

LQFP and SO NiPdAu (Nickel-palladium-Gold) Yes Yes *

ST7MC1xx/ST7MC2xx

290/309

14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in ROM

versions and in user programmable versions

(FLASH) as well as in factory coded versions

(FASTROM). ST7MC are ROM devices. ST7PMC

devices are Factory Advanced Service Technique

ROM (FASTROM) versions: they are programmed

Flash devices.

ST7FMC Flash devices are shipped to customers

with a default content (FFh), while ROM/FAS-

TROM factory coded parts contain the code sup-

plied by the customer. This implies that Flash de-

vices have to be configured by the customer using

the Option Bytes while the ROM devices are facto-

ry-configured.

14.1 FLASH OPTION BYTES

The option bytes allow the hardware configuration

of the microcontroller to be selected. They have no

address in the memory map and can be accessed

only in programming mode (for example using a

standard ST7 programming tool). The default con-

tent of the FLASH is fixed to FFh. This means that

all the options have “1” as their default value.

OPTION BYTE 0

OPT7= WDG HALT Watchdog and Halt mode

This option bit determines if a RESET is generated

when entering Halt mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = CKSEL Clock Source Selection.

0: PLL clock selected1)

1: Oscillator clock selected

Note 1: Even if PLL clock is selected, a clock signal must

always be present (refer to Figure 13. on page 28)

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection

block (LVD, and AVD).

OPT2 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

Halt mode. For resonator oscillators, it is advised

to select 4096 due to the long crystal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

Note: When the PLL clock is selected (CKSEL=0),

the reset clock cycle selection is forced to 4096

CPU cycles.

OPT1= DIV2 Divider by 2

1: DIV2 divider disabled with OSCIN = 8MHz

0: DIV2 divider enabled (in order to have 8 MHz re-

quired for the PLL with OSCIN =16 Mhz))

OPT0= FMP_R Flash memory read-out protection

Readout protection, when selected provides a pro-

tection against program memory content extrac-

tion and against write access to Flash memory.

This protection is based on a read/write protection

of the memory in test modes and ICP mode. Eras-

ing the option bytes when the FMP_R option is se-

lected causes the whole user memory to be

erased first and the device can be reprogrammed.

Refer to the ST7 Flash Programming Reference

Manual and section 4.3.1 on page 22 for more de-

tails.

0: Read-out protection enabled

1: Read-out protection disabled

STATIC OPTION BYTE 0

STATIC OPTION BYTE 1

WDG

CKSEL

RSTC

DIV2

FMP_R

PKG MCO

HALT

10 210

Default

value 111111111 1 111 1 11

Selected Low Voltage Detector VD1 VD0

LVD and AVD On 0 0

LVD On and AVD Off 0 1

LVD and AVD Off 10

Selected Low Voltage Detector VD1 VD0

ST7MC1xx/ST7MC2xx

291/309

ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPTION BYTE 1

OPT7:5= PKG[2:0] package selection

These option bits are used to select the device

package.

OPT4:2= Reserved

OPT1:0 = MCO Motor Control Output Options

MCO port under reset.

Selected Package PKG2 PKG1 PKG0

LQFP32 / SDIP32 0 0 0

LQFP44 0 0 1

SDIP 56 010

LQFP64 0 1 1

LQFP80 1 x x

Motor Control Output bit 1 bit 0

HiZ 0 0

Low 0 1

High 1 0

HiZ 1 1

ST7MC1xx/ST7MC2xx

292/309

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

The FASTROM or ROM contents are to be sent on

diskette, or by electronic means, with the hexadec-

imal file in .S19 format generated by the develop-

ment tool. All unused bytes must be set to FFh.

The selected options are communicated to STMi-

croelectronics using the correctly completed OP-

TION LIST appended.

Refer to Application Note AN1635 for information

on the counter listing returned by ST after code

has been transferred.

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on con-

tractual points.

Figure 167. Ordering information scheme

ST7 F MC1 K 2 T 6

Family

ST7 microcontroller family

Memory type

F: Flash

P: FASTROM

Memory size

2 = 8K

4 = 16K

6 = 32K

7 = 48K

9 = 60K

Package

T = LQFP

B = Plastic DIP

Example:

No. of pins

K = 32

S = 44

N = 56

R = 64

M = 80

Sub-family

MC1 or MC2

Temperature range

6 = -40 °C to 85 °C

3 = -40 °C to 125 °C

For a list of available options (e.g. memory size, package) and orderable part numbers or for further information

on any aspect of this device, please contact the ST Sales Office nearest to you.

ST7MC1xx/ST7MC2xx

293/309

ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

ST7MC MICROCONTROLLER OPTION LIST

(Last update: September 2008)

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference/ROM or FASTROM Code* : . . . . . . . . . . . .

*The ROM or FASTROM code name is assigned by STMicroelectronics.

ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.

Device type/memory size/package (check only one option):

Conditioning (check only one option):

Special Marking [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Temperature range [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C

MCO (Motor Control Output

state under reset) [ ] Hiz [ ] Low [ ] High

DIV2 [ ] Disabled [ ] Enabled

CKSEL [ ] Oscillator clock [ ] PLL clock

Watchdog Selection [ ] Software Activation [ ] Hardware Activation

Halt when Watchdog on [ ] Reset [ ] No reset

Readout Protection [ ] Disabled [ ] Enabled

LVD Reset [ ] Disabled [ ] Enabled

AVD Interrupt (if LVD enabled) [ ] Disabled [ ] Enabled

Reset Delay [ ] 256 Cycles [ ] 4096 Cycles

Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please download the latest version of this option list from:

http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

---------------

ROM

---------------

--------------------

-------------------

16K

-------------------

--------------------

32K

--------------------

-------------------

48K

-------------------

--------------------

60K

--------------------

LQFP32: | [ ] | | | | |

LQFP44: | | [ ] | | | |

---------------

FASTROM

---------------

--------------------

-------------------

16K

-------------------

--------------------

32K

--------------------

-------------------

48K

-------------------

--------------------

60K

--------------------

LQFP32: | [ ] | [ ] | | | |

LQFP44: | | [ ] | [ ] | | |

LQFP64: | | | [ ] | [ ] | |

LQFP80: | | | | | [ ] |

[ ] Tape & Reel [ ] Tray

ST7MC1xx/ST7MC2xx

294/309

ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.3 DEVELOPMENT TOOLS

Development tools for the ST7 microcontrollers in-

clude a complete range of hardware systems and

software tools from STMicroelectronics and third-

party tool suppliers. The range of tools includes

solutions to help you evaluate microcontroller pe-

ripherals, develop and debug your application, and

program your microcontrollers.

14.3.1 Starter kits

ST offers complete, affordable starter kits and

full-featured that allow you to evaluate microcon-

troller features and quickly start developing ST7

applications. Starter kits are complete hardware/

software tool packages that include features and

samples to to help you quickly start developing

your application.

14.3.2 Development and debugging tools

Application development for ST7 is supported by

fully optimizing C Compilers and the ST7 Assem-

bler-Linker toolchain, which are all seamlessly in-

tegrated in the ST7 integrated development envi-

ronments in order to facilitate the debugging and

fine-tuning of your application. The Cosmic C

Compiler is available in a free version that outputs

up to 16K of code.

The range of hardware tools includes full-featured

ST7-EMU2B series emulators and the low-cost

RLink in-circuit debugger/programmer. These

tools are supported by the ST7 Toolset from ST-

Microelectronics, which includes the STVD7 inte-

grated development environment (IDE) with high-

level language debugger, editor, project manager

and integrated programming interface.

14.3.3 Programming tools

During the development cycle, the ST7-EMU3 se-

ries emulators and the RLink provide in-circuit

programming capability for programming the Flash

microcontroller on your application board.

ST also provides a low-cost dedicated in-circuit

programmer, the ST7-STICK, as well as ST7

Socket Boards which provide all the sockets re-

quired for programming any of the devices in a

specific ST7 sub-family on a platform that can be

used with any tool with in-circuit programming ca-

pability for ST7.

For production programming of ST7 devices, ST’s

third-party tool partners also provide a complete

range of gang and automated programming solu-

tions, which are ready to integrate into your pro-

duction environment.

14.3.4 Order codes for ST7MC development tools

Table 91. Development tool order codes for the ST7MC family

1. Add suffix /EU, /UK or /US for the power supply for your region

2. Parallel port connection to PC

3. RLink with ST7 tool set

For additional ordering codes for spare parts and accessories, refer to the online product selector at

www.st.com/mcu.

MCU Starter kit Emulator Programming tool

ST7MC1

ST7MC2 ST7MC-KIT/BLDC ST7MDT50-EMU3 ST7-STICK1)2)

STX-RLINK3)

ST7MC1xx/ST7MC2xx

295/309

ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.3.5 PACKAGE/SOCKET FOOTPRINT PROPOSAL

Table 92. Suggested List of Socket Types

Package / Probe Socket Reference Emulator Adapter

LQFP64 14x14 CAB 3303262 CAB 3303351

LQFP80 14x14 YAMAICHI IC149-080-*51-*5 YAMAICHI ICP-080-7

LQFP32 7x7 IRONWOOD SF-QFE32SA-L-01 IRONWOOD SK-UGA06/32A-01

LQFP44 10x10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5

SDIP32 Standard Standard

SDIP56 Standard Standard

ST7MC1xx/ST7MC2xx

296/309

14.4 ST7 APPLICATION NOTES

Table 93. ST7 Application Notes

IDENTIFICATION DESCRIPTION

APPLICATION EXAMPLES

AN1658 SERIAL NUMBERING IMPLEMENTATION

AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS

AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555

AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI

AN1812 A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-

PUT VOLTAGES

EXAMPLE DRIVERS

AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC

AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM

AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM

AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION

AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE

AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION

AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER

AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)

AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT

AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER

AN1046 UART EMULATION SOFTWARE

AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS

AN1048 ST7 SOFTWARE LCD DRIVER

AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE

AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS

AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

AN1105 ST7 PCAN PERIPHERAL DRIVER

AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141

AN1130 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS

WITH THE ST72141

AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE

AN1149 HANDLING SUSPEND MODE ON A USB MOUSE

AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER

AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE

AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X

AN1445 EMULATED 16-BIT SLAVE SPI

AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION

AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER

AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS

AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS

AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART

AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS

AN1753 SOFTWARE UART USING 12-BIT ART

£7

ST7MC1xx/ST7MC2xx

297/309

AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY

GENERAL PURPOSE

AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES

AN1526 ST7FLITE0 QUICK REFERENCE NOTE

AN1709 EMC DESIGN FOR ST MICROCONTROLLERS

AN1752 ST72324 QUICK REFERENCE NOTE

PRODUCT EVALUATION

AN 910 PERFORMANCE BENCHMARKING

AN 990 ST7 BENEFITS VS INDUSTRY STANDARD

AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS

AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING

AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141

AN1150 BENCHMARK ST72 VS PC16

AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876

AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS

PRODUCT MIGRATION

AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324

AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B

AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264

AN2200 GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB

PRODUCT OPTIMIZATION

AN 982 USING ST7 WITH CERAMIC RESONATOR

AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE

AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES

AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY

AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT

AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS

AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY

AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY

AN1530 ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-

TOR

AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE

AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS

AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE

AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC

AN1953 PFC FOR ST7MC STARTER KIT

AN1971 ST7LITE0 MICROCONTROLLED BALLAST

PROGRAMMING AND TOOLS

AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES

AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE

AN 985 EXECUTING CODE IN ST7 RAM

AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7

AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING

AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN

AN1039 ST7 MATH UTILITY ROUTINES

Table 93. ST7 Application Notes

IDENTIFICATION DESCRIPTION

ST7MC1xx/ST7MC2xx

298/309

AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER

AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-

GRAMMING)

AN1446 USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION

AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY

AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR

AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS

AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS

AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL

AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)

AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION

AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC

AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT

AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL

AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY

AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY

SYSTEM OPTIMIZATION

AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS

AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09

AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC

AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

Table 93. ST7 Application Notes

IDENTIFICATION DESCRIPTION

ST7MC1xx/ST7MC2xx

299/309

15 IMPORTANT NOTES

15.1 FLASH/FASTROM DEVICES ONLY

The behaviors described in the following sections

are present on Rev A, B or C ST7FMC and

ST7PMC devices only.

They are identifiable:

- on the device package, by the last letter of the

Trace Code marked on the device package.

- on the box, by the last 3 digits of the Internal

Sales Type printed in the box label.

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