FSDH0265RN, FSDM0265RN Datasheet by ON Semiconductor

— FAIRCHILD — SEMiCQNDUCTQFw a? Vs|r Drain *|:HK gig Figure 1. Typical Flyback Application

www.fairchildsemi.com

Rev.1.0.6

Features

• Internal Avalanche Rugged Sense FET

• Consumes only 0.65W at 240VAC & 0.3W load with

Advanced Burst-Mode Operation

• Frequency Modulation for low EMI

• Precision Fixed Operating Frequency

• Internal Start-up Circuit

• Pulse by Pulse Current Limiting

• Abnormal Over Current Protection

• Over Voltage Protection

• Over Load Protection

• Internal Thermal Shutdown Function

• Auto-Restart Mode

• Under Voltage Lockout

• Low Operating Current (3mA)

• Adjustable Peak Current Limit

• Built-in Soft Start

Applications

• SMPS for VCR, SVR, STB, DVD & DVCD

• SMPS for Printer, Facsimile & Scanner

• Adaptor for Camcorder

Description

The FSDx0265RN(x stands for M, H) are integrated Pulse

Width Modulators (PWM) and Sense FETs specifically

designed for high performance offline Switch Mode Power

Supplies (SMPS) with minimal external components. Both

devices are integrated high voltage power switching regula-

tors which combine an avalanche rugged Sense FET with a

current mode PWM control block. The integrated PWM con-

troller features include: a fixed oscillator with frequency

modulation for reduced EMI, Under Voltage Lock Out

(UVLO) protection, Leading Edge Blanking (LEB), opti-

mized gate turn-on/turn-off driver, Thermal Shut Down

(TSD) protection, Abnormal Over Current Protection

(AOCP) and temperature compensated precision current

sources for loop compensation and fault protection circuitry.

When compared to a discrete MOSFET and controller or

RCC switching converter solution, the FSDx0265RN reduce

total component count, design size, weight and at the same

time increase efficiency, productivity, and system reliability.

Both devices are a basic platform well suited for cost effec-

tive designs of flyback converters.

Table 1. Notes: 1. Typical continuous power in a non-ven-

tilated enclosed adapter with sufficient drain pattern or

something as a heat sinker measured at 50°C ambient. 2.

Maximum practical continuous power in an open frame

design with sufficient drain pattern or something as a

heat sinker at 50°C ambient. 3. 230 VAC or 100/115 VAC

with doubler.

Typical Circuit

Figure 1. Typical Flyback Application

OUTPUT POWER TABLE

PRODUCT

230VAC ±15%(3) 85-265VAC

Adapt-

er(1)

Open

Frame(2)

Adapt-

er(1)

Open

Frame(2)

FSDL321 11W 17W 8W 12W

FSDH321 11W 17W 8W 12W

FSDL0165RN 13W 23W 11W 17W

FSDM0265RN 16W 27W 13W 20W

FSDH0265RN 16W 27W 13W 20W

FSDL0365RN 19W 30W 16W 24W

FSDM0365RN 19W 30W 16W 24W

FSDL321L 11W 17W 8W 12W

FSDH321L 11W 17W 8W 12W

FSDL0165RL 13W 23W 11W 17W

FSDM0265RL 16W 27W 13W 20W

FSDH0265RL 16W 27W 13W 20W

FSDL0365RL 19W 30W 16W 24W

FSDM0365RL 19W 30W 16W 24W

Drain

Source

Vstr

Vfb Vcc

PWM

IN DC

OUT

Ipk

FSDH0265RN, FSDM0265RN

Green Mode Fairchild Power Switch (FPSTM)

.M.‘D_A__uA_..uA_‘.m_‘.mA.‘__A.‘_..A.‘_‘.A.‘_‘._

FSDH0265RN, FSDM0265RN

Internal Block Diagram

Figure 2. Functional Block Diagram of FSDx0265RN

8V/12V

26,7,8

Vref Internal

Bias

OSC

Vcc Vcc

Idelay IFB

VSD

TSD

Vovp

Vcc

Vocp

2.5R

Vcc good

Vcc Drain

VFB

GND

AOCP

Gate

driver

Vstr

Istart

Vcc good

VBURL/VBURH

LEB

PWM

Soft start

Ipk

Freq.

Modulation

VBURH Vcc

IB_PEAK

Burst

Normal

FSDH0265RN, FSDM0265RN

Pin Definitions

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Number Pin Name Pin Function Description

1 GND Sense FET source terminal on primary side and internal control ground.

2Vcc

Positive supply voltage input. Although connected to an auxiliary transform-

er winding, current is supplied from pin 5 (Vstr) via an internal switch during

startup (see Internal Block Diagram section). It is not until Vcc reaches the

UVLO upper threshold (12V) that the internal start-up switch opens and de-

vice power is supplied via the auxiliary transformer winding.

3Vfb

The feedback voltage pin is the non-inverting input to the PWM comparator.

It has a 0.9mA current source connected internally while a capacitor and op-

tocoupler are typically connected externally. A feedback voltage of 6V trig-

gers over load protection (OLP). There is a time delay while charging

between 3V and 6V using an internal 5uA current source, which prevents

false triggering under transient conditions but still allows the protection

mechanism to operate under true overload conditions.

4Ipk

Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current

source is diverted to the parallel combination of an internal 2.8kΩ resistor

and any external resistor to GND on this pin to determine the current limit.

If this pin is tied to Vcc or left floating, the typical current limit will be 1.5A.

5Vstr

This pin connects directly to the rectified AC line voltage source. At start up

the internal switch supplies internal bias and charges an external storage

capacitor placed between the Vcc pin and ground. Once the Vcc reaches

12V, the internal switch is disabled.

6, 7, 8 Drain

The Drain pin is designed to connect directly to the primary lead of the trans-

former and is capable of switching a maximum of 650V. Minimizing the

length of the trace connecting this pin to the transformer will decrease leak-

age inductance.

8GND

Vcc

Vfb

Ipk Vstr

Drain

8DIP

8LSOP

FSDH0265RN, FSDM0265RN

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified)

Note:

1. Repetitive rating: Pulse width limited by maximum junction temperature

2. L = 51mH, starting Tj = 25°C

3. L = 13µH, starting Tj = 25°C

4. Vsd is shutdown feedback voltage ( see Protection Section in Electrical Characteristics )

Thermal Impedance

Note:

1. Free standing with no heatsink.

2. Measured on the DRAIN pin close to plastic interface.

3. Without copper clad.

4. Measured on the PKG top surface.

* - all items are tested with the standard JESD 51-10(DIP)

Characteristic Symbol Value Unit

Maximum Drain Pin Voltage VDRAIN,MAX 650V V

Maximum Vstr Pin Voltage VSTR,MAX 650V V

Drain Current Pulsed(1) IDM 8.0 ADC

Single Pulsed Avalanche Energy(2) EAS 68 mJ

Maximum Supply Voltage VCC,MAX 20 V

Analog Input Voltage Range VFB -0.3 to VCC V

Total Power Dissipation PD1.56 W

Operating Junction Temperature. TJInternally limited °C

Operating Ambient Temperature. TA-25 to +85 °C

Storage Temperature Range. TSTG -55 to +150 °C

Parameter Symbol Value Unit

8DIP

Junction-to-Ambient Thermal θJA(1) 79.64(3) °C/W

Junction-to-Case Thermal θJC(2) 18.20 °C/W

Junnction-to-Top Thermal ψJT(4) 34.30 °C/W

FSDH0265RN, FSDM0265RN

Electrical Characteristics

(Ta = 25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Sense FET SECTION

Off-State Current

(Max.Rating =660V) IDSS

VDS=660V, VGS=0V - - 50 µA

VDS=0.8Max.Rating,

VGS=0V, TC=125°C- - 200 µA

On-State Resistance(1) RDS(ON) VGS=10V, ID=0.5A - 5.0 6.0 Ω

Input Capacitance CISS

VGS=0V, VDS=25V,

F=1MHz

- 550 - pF

Output Capacitance COSS -38-pF

Reverse Transfer Capacitance CRSS -17-pF

Turn On Delay Time TD(ON)

VDS=325V, ID=1.0A

(Sense FET switching

time is essentially

independent of

operating temperature)

- 20 - ns

Rise Time TR - 15 - ns

Turn Off Delay Time TD(OFF) -55-ns

Fall Time TF -25-ns

CONTROL SECTION

Output Frequency FOSC

FSDH0265R

92 100 108 KHz

Output Frequency Modulation FMOD ±2.0 ±.3.0 ±4.0 KHz

Output Frequency FOSC

FSDM0265R

61 67 73 KHz

Output Frequency Modulation FMOD ±1.5 ±2.0 ±2.5 KHz

Frequency Change With Temperature(2) --25°C ≤ Ta ≤ 85°C - ±5 ±10 %

Maximum Duty Cycle DMAX

FSDH0265R 71 77 83 %

FSDM0265R 62 67 72 %

Minimum Duty Cycle DMIN 000%

Start threshold voltage VSTART V

FB=GND 11 12 13 V

Stop threshold voltage VSTOP V

FB=GND 7 8 9 V

Feedback Source Current IFB V

FB=GND 0.7 0.9 1.1 mA

Internal Soft Start Time TS/S V

FB=4V 10 15 20 ms

BURST MODE SECTION

Burst Mode Voltages

VBURH - 0.4 0.5 0.6 V

VBURL - 0.25 0.35 0.45 V

PROTECTION SECTION

Drain to Source Peak Current Limit IOVER Max. inductor current 1.3 1.5 1.7 A

Current Limit Delay(3) TCLD - 500 - ns

FSDH0265RN, FSDM0265RN

Note:

1. Pulse test: Pulse width ≤ 300uS, duty ≤ 2%

2. These parameters, although guaranteed, are tested in EDS (wafer test) process

3. These parameters, although guaranteed, are not 100% tested in production

Thermal Shutdown TSD - 125 140 - °C

Shutdown Feedback Voltage VSD 5.5 6.0 6.5 V

Over Voltage Protection VOVP 18 19 - V

Shutdown Feedback Delay Current IDELAY V

FB=4V 3.5 5.0 6.5 µA

Leading Edge Blanking Time TLEB 200 - - ns

TOTAL DEVICE SECTION

Operating Current IOP V

CC=14V 1 3 5 mA

Start Up Current ISTART V

CC=0V 0.7 0.85 1.0 mA

Vstr Supply Voltage VSTR VCC=0V 35 - - V

FSDH0265RN, FSDM0265RN

Comparison Between KA5x0265RN and FSDx0265RN

Function KA5x0265RN FSDx0265RN FSDx0265RN Advantages

Soft-Start not applicable 15mS • Gradually increasing current limit

during soft-start further reduces peak

current and voltage component

stresses

• Eliminates external components used

for soft-start in most applications

• Reduces or eliminates output

overshoot

External Current Limit not applicable Programmable of

default current limit

• Smaller transformer

• Allows power limiting (constant over-

load power)

• Allows use of larger device for lower

losses and higher efficiency.

Frequency Modulation not applicable ±2.0KHz @67KHz

±3.0KHz @100KHz

• Reduced conducted EMI

Burst Mode Operation not applicable Yes-built into

controller

• Improve light load efficiency

• Reduces no-load consumption

• Transformer audible noise reduction

Drain Creepage at

Package

1,02mm 7.62mm • Greater immunity to arcing as a result

of build-up of dust, debris and other

contaminants

FSDH0265RN, FSDM0265RN

Typical Performance Characteristics (Control Part)

(These characteristic graphs are normalized at Ta = 25°C)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Operating Frequency (Fosc)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Frequency Modulation (FMOD)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Maximum duty cycle (Dmax)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Operating supply current (Iop)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Nomalized

Start Threshold Voltage (Vstart)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Stop Threshold Voltage (Vstop)

FSDH0265RN, FSDM0265RN

Typical Performance Characteristics (Continued)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Feedback Source Current (Ifb)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Peak current limit (Iover)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Start up Current (Istart)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

J-FET Start up current (Istr)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Burst peak current (Iburst)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-50 0 50 100 150

Temp[℃]

Normalized

Over Voltage Protection (Vovp)

FSDH0265RN, FSDM0265RN

Functional Description

1. Startup : In previous generations of Fairchild Power

Switches (FPSTM) the Vstr pin had an external resistor to the

DC input voltage line. In this generation the startup resistor

is replaced by an internal high voltage current source and a

switch that shuts off when 15mS goes by after the supply

voltage, Vcc, gets above 12V. The source turns back on if

Vcc drops below 8V.

Figure 4. High voltage current source

2. Feedback Control : The FSDx0265RN employs current

mode control, shown in figure 5. An opto-coupler (such as

the H11A817A) and shunt regulator (such as the KA431) are

typically used to implement the feedback network. Compar-

ing the feedback voltage with the voltage across the Rsense

resistor plus an offset voltage makes it possible to control the

switching duty cycle. When the reference pin voltage of the

KA431 exceeds the internal reference voltage of 2.5V, the

H11A817A LED current increases, thus pulling down the

feedback voltage and reducing the duty cycle. This event

typically happens when the input voltage is increased or the

output load is decreased.

3. Leading edge blanking (LEB) : At the instant the inter-

nal Sense FET is turned on, there usually exists a high cur-

rent spike through the Sense FET, caused by the primary side

capacitance and secondary side rectifier diode reverse recov-

ery. Excessive voltage across the Rsense resistor would lead

to incorrect feedback operation in the current mode PWM

control. To counter this effect, the FPSTM employs a leading

edge blanking (LEB) circuit. This circuit inhibits the PWM

comparator for a short time (TLEB) after the Sense FET is

turned on.

Figure 5. Pulse width modulation (PWM) circuit

4. Protection Circuit : The FPSTM has several protective

functions such as over load protection (OLP), over voltage

protection (OVP), abnormal over current protection

(AOCP), under voltage lock out (UVLO) and thermal shut-

down (TSD). Because these protection circuits are fully inte-

grated inside the IC without external components, the

reliability is improved without increasing cost. Once the

fault condition occurs, switching is terminated and the Sense

FET remains off. This causes Vcc to fall. When Vcc reaches

the UVLO stop voltage, 8V, the protection is reset and the

internal high voltage current source charges the Vcc capaci-

tor via the Vstr pin. When Vcc reaches the UVLO start volt-

age,12V, the FPSTM resumes its normal operation. In this

manner, the auto-restart can alternately enable and disable

the switching of the power Sense FET until the fault condi-

tion is eliminated.

4.1 Over Load Protection (OLP) : Overload is defined as

the load current exceeding a pre-set level due to an unex-

pected event. In this situation, the protection circuit should

be activated in order to protect the SMPS. However, even

when the SMPS is in the normal operation, the over load

protection circuit can be activated during the load transition.

In order to avoid this undesired operation, the over load pro-

tection circuit is designed to be activated after a specified

time to determine whether it is a transient situation or an

overload situation. In conjunction with the Ipk current limit

pin (if used) the current mode feedback path would limit the

current in the Sense FET when the maximum PWM duty

cycle is attained. If the output consumes more than this max-

imum power, the output voltage (Vo) decreases below the set

voltage. This reduces the current through the opto-coupler

LED, which also reduces the opto-coupler transistor current,

thus increasing the feedback voltage (Vfb). If Vfb exceeds

3V, the feedback input diode is blocked and the 5uA Idelay

current source starts to charge Cfb slowly up to Vcc. In this

condition, Vfb continues increasing until it reaches 6V, when

the switching operation is terminated as shown in figure 6.

The delay time for shutdown is the time required to charge

Vin,dc

Vstr

Vcc

15mS After UVLO

start(>12V)

off

UVLO <8V

Istr

J-FET

3OSC

Vcc Vref

5uA 0.9mA

VSD

2.5R

Gate

driver

OLP

D1 D2

Vfb*

Vfb

431

Cfb

FSDH0265RN, FSDM0265RN

Cfb from 3V to 6V with 5uA.

Figure 6. Over load protection

4.2 Thermal Shutdown (TSD) : The Sense FET and the

control IC are integrated, making it easier for the control IC

to detect the temperature of the Sense FET. When the tem-

perature exceeds approximately 140°C, thermal shutdown is

activated.

4.3 Abnormal Over Current Protection (AOCP) :

Figure 7. AOCP Function & Block

Even though the FPSTM has OLP (Over Load Protection)

and current mode PWM feedback, these are not enough to

protect the FPSTM when a secondary side diode short or a

transformer pin short occurs. In addition to start-up, soft-

start is also activated at each restart attempt during auto-

restart and when restarting after latch mode is activated. The

FPSTM has an internal AOCP (Abnormal Over Current Pro-

tection) circuit as shown in figure 7. When the gate turn-on

signal is applied to the power Sense FET, the AOCP block is

enabled and monitors the current through the sensing resis-

tor. The voltage across the resistor is then compared with a

preset AOCP level. If the sensing resistor voltage is greater

than the AOCP level, pulse by pulse AOCP is triggered

regardless of uncontrollable LEB time. Here, pulse by pulse

AOCP stops Sense FET within 350nS after it is activated.

4.4 Over Voltage Protection (OVP) : In case of malfunc-

tion in the secondary side feedback circuit, or feedback loop

open caused by a defect of solder, the current through the

opto-coupler transistor becomes almost zero. Then, Vfb

climbs up in a similar manner to the over load situation, forc-

ing the preset maximum current to be supplied to the SMPS

until the over load protection is activated. Because excess

energy is provided to the output, the output voltage may

exceed the rated voltage before the over load protection is

activated, resulting in the breakdown of the devices in the

secondary side. In order to prevent this situation, an over

voltage protection (OVP) circuit is employed. In general,

Vcc is proportional to the output voltage and the FPSTM uses

Vcc instead of directly monitoring the output voltage. If

VCC exceeds 19V, OVP circuit is activated resulting in ter-

mination of the switching operation. In order to avoid undes-

ired activation of OVP during normal operation, Vcc should

be properly designed to be below 19V.

5. Soft Start : The FPSTM has an internal soft start circuit

that increases the feedback voltage together with the Sense

FET current slowly after it starts up. The typical soft start

time is 15msec, as shown in figure 8, where progressive

increments of Sense FET current are allowed during the

start-up phase. The pulse width to the power switching

device is progressively increased to establish the correct

working conditions for transformers, inductors, and capaci-

tors. The voltage on the output capacitors is progressively

increased with the intention of smoothly establishing the

required output voltage. It also helps to prevent transformer

saturation and reduce the stress on the secondary diode.

1t2t3t4tt

Vcc

Delay current (5uA) charges the Cfb

FPS switching

OLP

Following Vcc

2._

,8.2,3)1();

)1(

1figfbfb

CCKRVtV

t=Ω==−−=

VtVttVuAI

tVttV

Ct delay

delay

fb 3)1()21(,5;

))1()21((

2=−+=

−+

Vsense

Vfb

Out Dri ve r

Rsense

CLK

Drai n

AOCP

PWM

COMPARATOR

AOCP

COMPARATOR

LEB

1mS 15steps

Current limit

0.98A

2.15A

Drain cur rent

[A]

FSDH0265RN, FSDM0265RN

Figure 8. Soft Start Function

6. Burst operation :In order to minimize power dissipation

in standby mode, the FPSTM enters burst mode operation.

Figure 9. Circuit for Burst operation

As the load decreases, the feedback voltage decreases. As shown in

figure 10, the device automatically enters burst mode when the

feedback voltage drops below VBURH(500mV). Switching still con-

tinues but the current limit is set to a fixed limit internally to mini-

mize flux density in the transformer. The fixed current limit is

larger than that defined by Vfb = VBURH and therefore, Vfb is

driven down further. Switching continues until the feedback

voltage drops below VBURL(350mV). At this point switching

stops and the output voltages start to drop at a rate dependent

on the standby current load. This causes the feedback volt-

age to rise. Once it passes VBURH(500mV) switching resumes.

The feedback voltage then falls and the process repeats. Burst

mode operation alternately enables and disables switching of

the power Sense FET thereby reducing switching loss in

Standby mode.

Figure 10. Circuit for Burst Operation

7. Frequency Modulation : EMI reduction can be accom-

plished by modulating the switching frequency of a switched

power supply. Frequency modulation can reduce EMI by

spreading the energy over a wider frequency range than the

band width measured by the EMI test equipment. The

amount of EMI reduction is directly related to the depth of

the reference frequency. As can be seen in Figure 11, the fre-

quency changes from 65KHz to 69KHz in 4mS for the

FSDM0265RN. Frequency modulation allows the use of a

cost effective inductor instead of an AC input mode choke to

satisfy the requirements of world wide EMI limits.

Figure 11. Frequency Modulation Waveform

DRAIN

GND

Rsense

I_o ver

SWITCH

OFF

VBURL/

VBURH

VBURL

69kHz

67kHz

65kHz 4kHz

Turn-on Turn-off

point

Internal

Oscillator

Drain to

Source

voltage

Vds

Waveform

Drain to

Source

current

i rm w 54 m n , NW m ’V‘WU AV n; n i m m "WM 2 1 L4

FSDH0265RN, FSDM0265RN

Figure 12. KA5-series FPSTM Full Range EMI scan(67KHz,

no Frequency Modulation) with DVD Player SET

Figure 13. FSDX-series FPSTM Full Range EMI Scan

(67KHz, with Frequency Modulation) with DVD Player SET

8. Adjusting Current limit function: As shown in fig 14, a

combined 2.8kΩ internal resistance is connected into the

non-inverting lead on the PWM comparator. A external

resistance of A on the current limit pin forms a parallel resis-

tance with the 2.8kΩ when the internal diodes are biased by

the main current source of 900uA.

Figure 14. Peak current adjustment

For example, FSDx0265RN has a typical Sense FET current

limit (IOVER) of 1.5A. The Sense FET current can be limited

to 1A by inserting a 5.54kΩ between the current limit pin

and ground which is derived from the following equations:

1.5: 1 = 2.8KΩ : XkΩ ,

X = 1.86kΩ,

Since X represents the resistance of the parallel network, A

can be calculated using the following equation:

A = X / (1 - (X/2.8kΩ))

Frequency (MHz)

Amplitude (dBµV)

CISPR2QB

CISPR2AB

Frequency (MHz)

Amplitude (dBµV)

CISPR2QB

CISPR2AB

PWM

comparator

SenseFET

Sense

Ω

ΩK8.0

Ω

900uA

5uA

Rsense

Feed

Back

Current

Limit

FSDH0265RN, FSDM0265RN

Typical application circuit

1. Set Top Box Example Circuit (17W Output Power)

Figure15. 17W multiple power supply using FSDM0265RN

FSDM0265RN

DDD

SVccVfb

400V

/47u

UF4007

47K

UF4004

33n

50V

I_pk

start

6.8n/1k

30R

50V

47uF

D15

SB360

D14

D13

EGP20D

D12

PC817

FOD2741A

C11 C12

+3.3V

+5.0V

+17.0V

+23.0V

0.4~1.0A

0.2~0.7A

0.01~0.3A

0.005~0.25A

C13

C15

C17

C16

C14

1000uF

/16V

470uF

/10V

1000uF

/16V

470uF

/10V

470uF

/35V

220uF

/35V

100uF

/50V

100uF

/50V

R21 R14

R13

R15

330R 800R

6.9K R12

2.7K

1.5K

C209

0.1uF/mon

olithic

LF1

40mH KBP06M

100pF

/400V

100pF

/400V

2A/250V

FUSE

85VAC

~275VAC

56K/1/

R19

R20

PC817

TL431AZ

EGP20D

PERFORMANCE SUMMARY

Output Power: 17W

Regulation

3.3V: ±5%

5.0V: ±5%

17.0V: ±7%

23.0: ±7%

Efficiency: ≥75%

No load Consumption:

0.12W at 230Vac

GreenFPS

6kR

R15

20R

R22

1KR

ZD1

19V

ZD2

19V

Multiple Output, 17W, 85-265VAC Input Power supply:

Figure 15 shows a multiple output supply typical for high

end set-top boxes containing high capacity hard disks for

recording. The supply delivers an output power of 17W

cont./20 W peak (thermally limited) from an input voltage of

85 to 265 VAC. Efficiency at 12W, 85VAC is ≥75%.

The 3.3 V and 5 V outputs are regulated to ±5% without the

need for secondary linear regulators. DC stacking (the sec-

ondary winding reference for the other output voltages is

connected to the anode of D15. For more accuracy, connec-

tion to the cathode of D15 will be better.) is used to minimize

the voltage error for the higher voltage outputs. Due to the

high ambient operating temperature requirement typical of a

set-top box (60 °C) the FSDL0165RN is used to reduce con-

duction losses without a heatsink. Resistor R5 sets the device

current limit to limit overload power.

Leakage inductance clamping is provided by R1 and C8,

keeping the DRAIN voltage below 650 V under all condi-

tions. Resistor R1 and capacitor C8 are selected such that R1

dissipates power to prevent rising of DRAIN Voltage caused

by leakage inductance. The frequency modulation feature of

FSDL0165RN allows the circuit shown to meet CISPR2AB

with simple EMI filtering (C1, LF1 and C2) and the output

grounded. The secondaries are rectified and smoothed by

D12, D13, D14,and D15. Diode D15 for the 3.4V output is a

Schottky diode to maximize efficiency. Diode D14 for the 5

V output is a PN type to center the 5 V output at 5 V. The 3.3

V and 5 V output voltage require two capacitors in parallel to

meet the ripple current requirement. Switching noise filter-

ing is provided by L3, L2 and L1. Resistor R15 prevents

peak charging of the lightly loaded 23V output. The outputs

are regulated by the reference (TL431) voltage in secondary.

Both the 3.3 V and 5 V outputs are sensed via R13 and R14.

Resistor R22 provides bias for TL431and R21 sets the over-

all DC gain. Resistor R21, C209, R14 and R13 provide loop

compensation.

FSDH0265RN, FSDM0265RN

2. Transformer Specification

1. TRANSFORMER SPECIFICATION

- SCHEMATIC DIAGRAM (TRANSFORMER)

2. WINDING SPECIFICATION

NO. PIN(S → F) WIRE TURNS WINDING METHOD

NP/2 3 → 2 0.25 Φ × 1 22 SOLENOID WINDING

N3.3V 6 → 8 0.3 Φ × 8 2 STACK WINDING

N5V 10 → 6 0.3 Φ × 2 1 STACK WINDING

N16V 11 → 6 0.3 Φ × 4 7 SOLENOID WINDING

N23V 12 → 11 0.3 Φ × 2 3 SOLENOID WINDING

NP/2 2 → 1 0.25 Φ × 1 22 SOLENOID WINDING

NB 4 → 5 0.25 Φ × 1 10 CENTER WINDING

3. ELECTRIC CHARACTERISTIC

CLOSURE PIN SPEC. REMARKS

INDUCTANCE 1 - 3 800uH ± 10% 1KHz, 1V

LEAKAGE L 1 - 3 15uH MAX. 2nd ALL SHORT

4. BOBBIN & CORE.

CORE: EER2828

BOBBIN: EER2828

NP/2

N3.3V

NP/2

3mm

6mm

bottom top

N5V

N23V

N17V

’ ""‘1l’-I:O

FSDH0265RN, FSDM0265RN

Layout Considerations

Figure 15. Layout Considerations for FSDx0265RN using 8DIP

#1 : GND

#2 : VCC

#3 : Vfb

#4 : Ipk

#5 : Vstr

#6 : Drain

#7 : Drain

#8 : Drain

SURFACE MOUNTED

COPPER AREA FOR HEAT

SINKING

Y1-

CAPACITOR

OUT

DC_link Capacitor

NOTES: UNLESS OTHERWISE SPECIFIED A) nus Pm OONFORMB To JEDEC usom VARIATION BA 3) Au. DIMENSIONS ARE IN MILLIMEI'ERS. chENSIONSARE EXCLUSIVE 0F Bum. Mom HASH. AND TIE BAREXI'R‘USIWS. n) DIMENSIONS AND ms pm ASIE Yuan-1m MIKT-NOBFravB

FSDH0265RN, FSDM0265RN

Package Dimensions

8DIP

,90 .30 (11,55) L754 * LAND PAWERN RECOMMENDAT‘ON rggg , 3,70 MAX SEE DUAL A 0,10 MW I H' R020 R010 GAGE PLANE NOTES: UNLESS OTHERWLSE SRECIELED A) THLS PACKAGE DOESNOT CONFORM TO ANY CURRENT PACKAGE STANDARD 5) ALL DIMENSLONS ARE LN MILLLMETERS f c) DLMENSIoNs ARE EXCLUSIVE 0E EURRS‘ MOLD FLASH, AND HE EAR EXTRUSIONS, SEAT‘NG D) DLMENSLobs AND roLERANcES PER PLANE * ISME “4344994 ~—-—1.6D REE W SCALE. 2x

FSDH0265RN, FSDM0265RN

Package Dimensions (Continued)

8LSOP

FSDH0265RN, FSDM0265RN

Ordering Information

Product Number Package Marking Code BVDSS FOSC RDS(on)

FSDM0265RN 8DIP DM0265R 650V 67KHz 5.0Ω

FSDH0265RN 8DIP DH0265R 650V 100KHz 5.0Ω

FSDM0265RL 8LSOP DM0265R 650V 67KHz 5.0Ω

FSDH0265RL 8LSOP DH0265R 650V 100KHz 5.0Ω

FSDH0265RN, FSDM0265RN

4/26/05 0.0m 001

 2005 Fairchild Semiconductor Corporation

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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